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    <title>i.MX ProcessorsのトピックRe: i.mx6 dual with (2) MT41K256M16 DDR3L</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-dual-with-2-MT41K256M16-DDR3L/m-p/1018897#M150692</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;Hello,&lt;/P&gt;&lt;P class=""&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; Generally signals CS0, ODT0, SDCKE0 relate to the CS0 channel ; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;signals CS1, ODT1, SDCKE1 relate to the CS1 channel.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp;&amp;nbsp; Clock signals SDCLK0 and SDCLK1 in default state are the same and can be used &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;for both CS0 or CS1 channels if this makes easier PCB design.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp; So, if both MT41K256M16 parts are connected in parallel in order to form 32-bit data&lt;/P&gt;&lt;P class=""&gt;port - use common CS0, ODT0, SDCKE0, SDCLK0 for both.&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P class=""&gt;&lt;/P&gt;&lt;P class=""&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;P class=""&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt;Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 08 Nov 2019 03:33:02 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2019-11-08T03:33:02Z</dc:date>
    <item>
      <title>i.mx6 dual with (2) MT41K256M16 DDR3L</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-dual-with-2-MT41K256M16-DDR3L/m-p/1018896#M150691</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;We are planning on configuring an i.mx6 dual with (2)&amp;nbsp;MT41K256M16 DDR3L memories.&amp;nbsp; I can't find an eval version with this configuration; most have 4 devices.&amp;nbsp; I have just a few simple connections to verify:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1.&amp;nbsp; It appears that the two SDCLKs from the i.mx6 are identical so I should be able to connect one to each DDR chip for routing purposes, correct?&amp;nbsp; Normally, with 4 DDR chips each clock is connected to two DDR chips.&lt;/P&gt;&lt;P&gt;2.&amp;nbsp; When using the two SDCLKs, one for each DDR chip, I should use the corresponding SDCKE, correct? So SDCLK0 gets SDCLKE0, and SDCLK1 gets SDCLKE1.&lt;/P&gt;&lt;P&gt;3.&amp;nbsp; Should ODT0 and ODT1 be routed to both DDR chips, or simply use ODT0 for both?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for responding!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 07 Nov 2019 15:11:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-dual-with-2-MT41K256M16-DDR3L/m-p/1018896#M150691</guid>
      <dc:creator>dmatthews</dc:creator>
      <dc:date>2019-11-07T15:11:31Z</dc:date>
    </item>
    <item>
      <title>Re: i.mx6 dual with (2) MT41K256M16 DDR3L</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx6-dual-with-2-MT41K256M16-DDR3L/m-p/1018897#M150692</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;Hello,&lt;/P&gt;&lt;P class=""&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; Generally signals CS0, ODT0, SDCKE0 relate to the CS0 channel ; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;signals CS1, ODT1, SDCKE1 relate to the CS1 channel.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp;&amp;nbsp; Clock signals SDCLK0 and SDCLK1 in default state are the same and can be used &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: 'Verdana','sans-serif';"&gt;for both CS0 or CS1 channels if this makes easier PCB design.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp; So, if both MT41K256M16 parts are connected in parallel in order to form 32-bit data&lt;/P&gt;&lt;P class=""&gt;port - use common CS0, ODT0, SDCKE0, SDCLK0 for both.&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P class=""&gt;&lt;/P&gt;&lt;P class=""&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;&lt;P class=""&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt;Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 08 Nov 2019 03:33:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx6-dual-with-2-MT41K256M16-DDR3L/m-p/1018897#M150692</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2019-11-08T03:33:02Z</dc:date>
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