i.MX6ULL NAND DELAY timing

sugiyamatoshihi — Wed, 12 Feb 2020 08:05:46 GMT

Hi,

I have a question about NAND timing delay calculation RDN_DELAY in GPMI_CTRL1 of i.MX6ULL reference manual.

There is a description of example in page 1379 -1380 of i.MX 6ULL Applications Processor Reference Manual, Rev. 1, 11/2017.

"For example, a NAND with tREAmax = 20 ns, tRPmin = 12 ns, and tRCmin = 25 ns
(read cycle time) may be programmed as follows:
• GPMICLK clock frequency: Consider 480/6 = 80 MHz which is 12.5 ns clock
period. This is too close to the minimum NAND spec if we program the data setup
and hold to 1 GPMICLK cycle. Consider 480/7=68.57 MHz which is 14.58 ns clock
period. With data setup and hold set to 1, we have a tRP of 14.58ns and a tRC of
29.16 ns (good margins).
• Since (tREA +4ns) is greater than tRP, required DELAY = tREA + 4ns - tRP = 20 +
4 - 14.58ns = 9.42 ns.
• GPMI_CTRL1[HALF_PERIOD] =, since GPMICLK period is ns. So
RP=GPMICLK period = ns.
• DELAY = GPMI_CTRL1[RDN_DELAY] x 0.125 x RP. 9.42 ns =
GPMI_CTRL1[RDN_DELAY] x 0.125 x ns. GPMI_CTRL1[RDN_DELAY] =

However, in the last two paragraph, some data are missing.

Is it correct below red bold numbers?

• GPMI_CTRL1[HALF_PERIOD] =0, since GPMICLK period is 14.58 ns. So
RP=GPMICLK period = 14.58 ns.

• DELAY = GPMI_CTRL1[RDN_DELAY] x 0.125 x RP.

9.42 ns =GPMI_CTRL1[RDN_DELAY] x 0.125 x 14.58 ns.

GPMI_CTRL1[RDN_DELAY] =5.169=[0101b]

Best Regards,

Sugiyama

Re: i.MX6ULL NAND DELAY timing

Yuri — Mon, 17 Feb 2020 08:53:27 GMT

Hello,

Your understanding is correct.

Have a great day,

Yuri.

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i.MX6ULL NAND DELAY timing

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