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    <title>i.MX Processorsのトピック6ull ddr3 configuration</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/6ull-ddr3-configuration/m-p/1011747#M149826</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, we used nxp 6ull and winbond ddr3(w631GG6mb).The system occasionally crashes .We did not encounter this problem when using Samsung ddr3. Winbond engineers are helping to solve this problem.&lt;BR /&gt;When Winbond engineers deal with the problem,he need a memory configuration so that the memory clock keeps output.We have tried 21B_0004H [15:8] set to 0 ,and 21B_0404H [0] set to 1. But the memory clock still has a break.How do I set registers to keep the memory clock uninterrupted?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/94522i7080C47317BFDAC0/image-size/large?v=v2&amp;amp;px=999" title="ddrclk.png" alt="ddrclk.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 20 Nov 2019 00:21:53 GMT</pubDate>
    <dc:creator>lvjz</dc:creator>
    <dc:date>2019-11-20T00:21:53Z</dc:date>
    <item>
      <title>6ull ddr3 configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/6ull-ddr3-configuration/m-p/1011747#M149826</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, we used nxp 6ull and winbond ddr3(w631GG6mb).The system occasionally crashes .We did not encounter this problem when using Samsung ddr3. Winbond engineers are helping to solve this problem.&lt;BR /&gt;When Winbond engineers deal with the problem,he need a memory configuration so that the memory clock keeps output.We have tried 21B_0004H [15:8] set to 0 ,and 21B_0404H [0] set to 1. But the memory clock still has a break.How do I set registers to keep the memory clock uninterrupted?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/94522i7080C47317BFDAC0/image-size/large?v=v2&amp;amp;px=999" title="ddrclk.png" alt="ddrclk.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 20 Nov 2019 00:21:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/6ull-ddr3-configuration/m-p/1011747#M149826</guid>
      <dc:creator>lvjz</dc:creator>
      <dc:date>2019-11-20T00:21:53Z</dc:date>
    </item>
    <item>
      <title>Re: 6ull ddr3 configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/6ull-ddr3-configuration/m-p/1011748#M149827</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;About the DDR configuration you can use the script &lt;A href="https://community.nxp.com/docs/DOC-333791"&gt;https://community.nxp.com/docs/DOC-333791&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 20 Nov 2019 07:19:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/6ull-ddr3-configuration/m-p/1011748#M149827</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2019-11-20T07:19:18Z</dc:date>
    </item>
    <item>
      <title>Re: 6ull ddr3 configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/6ull-ddr3-configuration/m-p/1011749#M149828</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We have used the script to configurate the DDR3 . I’d like to know which&amp;nbsp;register and how to config&amp;nbsp; so that&amp;nbsp;&amp;nbsp;&amp;nbsp;I can&amp;nbsp;keep the&amp;nbsp;DDR3&amp;nbsp;clock uninterrupted. We tried disable&amp;nbsp;&amp;nbsp;MAPSR[PSD], MDPDC[PWDT_1], MDPDC[PWDT_0], MDPDC[PRCT_0],MDPDC[PRCT_1]. ,but these don't work .&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 20 Nov 2019 07:59:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/6ull-ddr3-configuration/m-p/1011749#M149828</guid>
      <dc:creator>lvjz</dc:creator>
      <dc:date>2019-11-20T07:59:13Z</dc:date>
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