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    <title>topic Re: i.MX 6ULL Ethernet RMII Interface Issue in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-6ULL-Ethernet-RMII-Interface-Issue/m-p/1010103#M149603</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for you feedback.&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 11 Mar 2020 07:31:03 GMT</pubDate>
    <dc:creator>jilujohn</dc:creator>
    <dc:date>2020-03-11T07:31:03Z</dc:date>
    <item>
      <title>i.MX 6ULL Ethernet RMII Interface Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-6ULL-Ethernet-RMII-Interface-Issue/m-p/1010099#M149599</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We have used the NXP processor, MCIMX6Y2CVM08AB (i.MX 6ULL) in our design. We are having an issue with ethernet interface using TI PHY (DP83849I). The connection is as follows.&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;RMII&amp;nbsp;&lt;/LI&gt;&lt;LI&gt;Clock is driven by PHY to Processor&lt;EM&gt; (Pin Name: &lt;STRONG&gt;ENET1_TX_CLK&lt;/STRONG&gt;, Muxed Pin: &lt;STRONG&gt;ENET1_REF_CLK&lt;/STRONG&gt;)&lt;/EM&gt;&lt;/LI&gt;&lt;LI&gt;All other connections are similar to the NXP reference board except the 50Mhz clock.&amp;nbsp;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;Attached the block diagram of the clock connection also the related schematic pages.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please confirm if connections are correct and the processor Pin (ENET1_TX_CLK) can work as an input. Also are there any configurations in software required for proper functioning of this interface. Please advice.&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Mar 2020 06:35:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-6ULL-Ethernet-RMII-Interface-Issue/m-p/1010099#M149599</guid>
      <dc:creator>jilujohn</dc:creator>
      <dc:date>2020-03-10T06:35:22Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX 6ULL Ethernet RMII Interface Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-6ULL-Ethernet-RMII-Interface-Issue/m-p/1010100#M149600</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Jilu&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes clock may be provided externally, one can look at uboot function setup_fec()&lt;/P&gt;&lt;P&gt;and IOMUXC_GPR_GPR1, bits ENET_CLK_SEL description in reference manual&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/mx6ullevk/mx6ullevk.c?h=imx_v2019.04_4.19.35_1.1.0" title="https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/mx6ullevk/mx6ullevk.c?h=imx_v2019.04_4.19.35_1.1.0"&gt;mx6ullevk.c\mx6ullevk\freescale\board - uboot-imx - i.MX U-Boot&lt;/A&gt;&lt;/P&gt;&lt;P&gt;Also may be useful:&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/440985"&gt;Ethernet problem with i.MX 7Dual and DP83849IVS PHY&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Mar 2020 10:11:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-6ULL-Ethernet-RMII-Interface-Issue/m-p/1010100#M149600</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-03-10T10:11:48Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX 6ULL Ethernet RMII Interface Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-6ULL-Ethernet-RMII-Interface-Issue/m-p/1010101#M149601</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your response.&amp;nbsp;&lt;/P&gt;&lt;P&gt;We have already checked the same.&lt;/P&gt;&lt;P&gt;Could you please check whether our schematics connections are correct or not.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Mar 2020 13:18:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-6ULL-Ethernet-RMII-Interface-Issue/m-p/1010101#M149601</guid>
      <dc:creator>jilujohn</dc:creator>
      <dc:date>2020-03-10T13:18:20Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX 6ULL Ethernet RMII Interface Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-6ULL-Ethernet-RMII-Interface-Issue/m-p/1010102#M149602</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Jilu&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;I think schematic is correct.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Mar 2020 01:05:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-6ULL-Ethernet-RMII-Interface-Issue/m-p/1010102#M149602</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-03-11T01:05:36Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX 6ULL Ethernet RMII Interface Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-6ULL-Ethernet-RMII-Interface-Issue/m-p/1010103#M149603</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for you feedback.&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Mar 2020 07:31:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-6ULL-Ethernet-RMII-Interface-Issue/m-p/1010103#M149603</guid>
      <dc:creator>jilujohn</dc:creator>
      <dc:date>2020-03-11T07:31:03Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX 6ULL Ethernet RMII Interface Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-6ULL-Ethernet-RMII-Interface-Issue/m-p/1010104#M149604</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;After setting the&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;IOMUXC_GPR_GPR1 registers bits 13, 14, 17, 18 in U-boot only we are able to note the increase in TX and RX bytes for both the Ethernet interfaces while giving ifconfig command.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;We connected our board to the laptop via the Ethernet port by creating a static IP connection between those two. When we try to ping the laptop from the board, we are able to ping from only one Ethernet interface and in another Ethernet interface we are not able to ping. When we checked the packets transferred in the interface in laptop using Wireshark, we found that the laptop is also replying to the ping request coming from the 2nd Ethernet interface but in the board's console there is no ping success prints.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;So, please advice us any if configuration change is needed for the 2nd Ethernet interface to work correctly.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Mar 2020 09:44:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-6ULL-Ethernet-RMII-Interface-Issue/m-p/1010104#M149604</guid>
      <dc:creator>jilujohn</dc:creator>
      <dc:date>2020-03-11T09:44:42Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX 6ULL Ethernet RMII Interface Issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-6ULL-Ethernet-RMII-Interface-Issue/m-p/1010105#M149605</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Jilu&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;may be useful to look on &lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/481957"&gt;i.MX6ULL using both ethernet ports, but ENET1 won't work&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Mar 2020 11:07:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-6ULL-Ethernet-RMII-Interface-Issue/m-p/1010105#M149605</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-03-11T11:07:09Z</dc:date>
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