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    <title>i.MX Processors中的主题 MSCALE debug options - Custom i.MX8MM DDR3L</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/MSCALE-debug-options-Custom-i-MX8MM-DDR3L/m-p/1007895#M149327</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have a custom board with the i.MX8M Mini and DDR3L memory that I'm trying to connect to the MSCALE tool for DRAM training. What debug options are available? Should&amp;nbsp;I see this tool connect to the A53 before any memory tests are even run?&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;I don't believe the tool is connecting to the A53 correctly because the Gen Code/Calibrate options are not available and the only output I see is the following:&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;PRE&gt;Downloading file 'bin\ddr3_imem_1d.bin' ..Done
Downloading file 'bin\ddr3_dmem_1d.bin' ..Done
Downloading file 'bin\ddr3_train_string.bin' ..Done
Downloading IVT header...Done
Downloading file 'bin\m845s_ddr_stress_test.bin' ...Done&lt;/PRE&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;BR /&gt;I've confirmed the following:&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;1. Connected to USB1, it enumerates as a HID device in Windows&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;2. Boot mode pins are set for serial download&lt;BR /&gt;3. UART2 pin mux is set in the script file&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;4. Connected to the A53 via JTAG to confirm it's running&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;My pin muxing is as follows:&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;SAI3_TXC -&amp;gt; UART2_TX&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;SAI3_TXFS -&amp;gt; UART2_RX&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;memory set 0x303301D8 32 0x00000004 #IOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS (UART2_RX)&lt;BR /&gt;memory set 0x303301DC 32 0x00000004 #IOMUXC_SW_MUX_CTL_PAD_SAI3_TXC (UART2_TX)&lt;BR /&gt;memory set 0x30330440 32 0x00000016 #IOMUXC_SW_PAD_CTL_PAD_SAI3_TXFS (UART2_RX)&lt;BR /&gt;memory set 0x30330444 32 0x00001816 #IOMUXC_SW_PAD_CTL_PAD_SAI3_TXC (UART2_TX)&lt;BR /&gt;memory set 0x303304FC 32 0x00000002 #IOMUXC_SW_MUX_UART2_SEL_RXD&lt;BR /&gt;sysparam set debug_uart 1 #UART index from 0 ('0' = UART1, '1' = UART2, '2' = UART3, '3' = UART4)&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 05 Nov 2019 14:54:55 GMT</pubDate>
    <dc:creator>tberryhill</dc:creator>
    <dc:date>2019-11-05T14:54:55Z</dc:date>
    <item>
      <title>MSCALE debug options - Custom i.MX8MM DDR3L</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MSCALE-debug-options-Custom-i-MX8MM-DDR3L/m-p/1007895#M149327</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have a custom board with the i.MX8M Mini and DDR3L memory that I'm trying to connect to the MSCALE tool for DRAM training. What debug options are available? Should&amp;nbsp;I see this tool connect to the A53 before any memory tests are even run?&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;I don't believe the tool is connecting to the A53 correctly because the Gen Code/Calibrate options are not available and the only output I see is the following:&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;PRE&gt;Downloading file 'bin\ddr3_imem_1d.bin' ..Done
Downloading file 'bin\ddr3_dmem_1d.bin' ..Done
Downloading file 'bin\ddr3_train_string.bin' ..Done
Downloading IVT header...Done
Downloading file 'bin\m845s_ddr_stress_test.bin' ...Done&lt;/PRE&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;BR /&gt;I've confirmed the following:&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;1. Connected to USB1, it enumerates as a HID device in Windows&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;2. Boot mode pins are set for serial download&lt;BR /&gt;3. UART2 pin mux is set in the script file&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;4. Connected to the A53 via JTAG to confirm it's running&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;My pin muxing is as follows:&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;SAI3_TXC -&amp;gt; UART2_TX&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;SAI3_TXFS -&amp;gt; UART2_RX&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;memory set 0x303301D8 32 0x00000004 #IOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS (UART2_RX)&lt;BR /&gt;memory set 0x303301DC 32 0x00000004 #IOMUXC_SW_MUX_CTL_PAD_SAI3_TXC (UART2_TX)&lt;BR /&gt;memory set 0x30330440 32 0x00000016 #IOMUXC_SW_PAD_CTL_PAD_SAI3_TXFS (UART2_RX)&lt;BR /&gt;memory set 0x30330444 32 0x00001816 #IOMUXC_SW_PAD_CTL_PAD_SAI3_TXC (UART2_TX)&lt;BR /&gt;memory set 0x303304FC 32 0x00000002 #IOMUXC_SW_MUX_UART2_SEL_RXD&lt;BR /&gt;sysparam set debug_uart 1 #UART index from 0 ('0' = UART1, '1' = UART2, '2' = UART3, '3' = UART4)&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 05 Nov 2019 14:54:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MSCALE-debug-options-Custom-i-MX8MM-DDR3L/m-p/1007895#M149327</guid>
      <dc:creator>tberryhill</dc:creator>
      <dc:date>2019-11-05T14:54:55Z</dc:date>
    </item>
    <item>
      <title>Re: MSCALE debug options - Custom i.MX8MM DDR3L</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MSCALE-debug-options-Custom-i-MX8MM-DDR3L/m-p/1007896#M149328</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Tyler&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;unfortunately using jtag for dram training and ddr test is not supported,&lt;/P&gt;&lt;P&gt;also there is no "jtag" option in description of &lt;A href="https://community.nxp.com/docs/DOC-340179"&gt;https://community.nxp.com/docs/DOC-340179&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 05 Nov 2019 23:18:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MSCALE-debug-options-Custom-i-MX8MM-DDR3L/m-p/1007896#M149328</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-11-05T23:18:41Z</dc:date>
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