topic Re: i.MX8QXP CSI-PIXEL_CLK_POL behavior in i.MX Processors

i.MX8QXP CSI-PIXEL_CLK_POL behavior

mamorukanou — Mon, 09 Mar 2020 13:37:25 GMT

Hello community,

We are connecting a Parallel camera to the CSI interface of i.MX8QXP and trying to capture video.
We are studying the setup time and hold time of each signal for the image input clock of i.MX8QXP. Please tell me about the input clock and the timing of HSYNC input, VSYNC input and data input.
Q)
Is the equivalent circuit of VSYNC_POL, HSYNC_POL, and PIXEL_CLK_POL of the CSI_CTRL_REG_CLR register considered as shown in the attached figure?

BestRegards,

Kanou

Re: i.MX8QXP CSI-PIXEL_CLK_POL behavior

nxf54947 — Mon, 23 Mar 2020 18:35:09 GMT

Hello kanou_mamoru@tte.toyotsu.net‌,

I will have to ask you to please contact your DBM (Distributor Business Manager) for assistance regarding the i.MX 8QXP. As this processor continues in preproduction, its peripheral settings and documentation may change in near future.

My apologies for the inconvenience this may cause to you.

Kind regards,

Ruben

Re: i.MX8QXP CSI-PIXEL_CLK_POL behavior

mamorukanou — Tue, 24 Mar 2020 00:11:14 GMT

Hi Ruben,

I got it. I'll ask NXP Japan FAE.

Thanks,

BR, Kanou