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    <title>i.MX ProcessorsのトピックRe: How does the scu interact with m4 or Acore?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/How-does-the-scu-interact-with-m4-or-Acore/m-p/1003671#M148755</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hi,igorpadykov&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;First of all, thank you for your quick reply!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;According to the documentation, the scu interacts with m4 primarily through ipc. In the scfw_api,the communication function is found:&lt;/P&gt;&lt;P&gt;1.ipc_read();&lt;/P&gt;&lt;P&gt;2.ipc_write();&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Through these functions, the communication link from m4 to scu can be realized.&amp;nbsp;However, the communication from scu to m4 failed.&amp;nbsp;Can you provide a more detailed example of communication from scu to m4?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR,&lt;/P&gt;&lt;P&gt;liwan special.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 25 Feb 2020 14:07:38 GMT</pubDate>
    <dc:creator>189659318</dc:creator>
    <dc:date>2020-02-25T14:07:38Z</dc:date>
    <item>
      <title>How does the scu interact with m4 or Acore?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-does-the-scu-interact-with-m4-or-Acore/m-p/1003669#M148753</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hello,&lt;/P&gt;&lt;P&gt;RT, in the imx8qm,&amp;nbsp; how does the scu interact with m4 or Acore?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the m4 SDK, it can be seen that m4 communicates with the scu&amp;nbsp;by the following APIs:&lt;/P&gt;&lt;P&gt;1.sc_misc_set_control ();&lt;/P&gt;&lt;P&gt;2.sc_misc_get_control ();&lt;/P&gt;&lt;P&gt;The api1: sc_misc_set_control ();After testing, the communication between m4 and scu can be realized.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Now, I want the scu would reply to m4 when it receives the message from m4. Similar logic has not been found in the SDK....so, I want to ask&amp;nbsp;how does scu send messages to m4 ?&amp;nbsp; Can you provide the demo?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 24 Feb 2020 08:06:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-does-the-scu-interact-with-m4-or-Acore/m-p/1003669#M148753</guid>
      <dc:creator>189659318</dc:creator>
      <dc:date>2020-02-24T08:06:31Z</dc:date>
    </item>
    <item>
      <title>Re: How does the scu interact with m4 or Acore?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-does-the-scu-interact-with-m4-or-Acore/m-p/1003670#M148754</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi livan &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;scu interacion is described in sect.2.2 System Controller Linux Manual&lt;/P&gt;&lt;P&gt;included in &lt;A href="https://www.nxp.com/webapp/Download?colCode=L4.19.35_1.1.0_LINUX_DOCS" target="_blank"&gt;Linux 4.19.35_1.1.0 Documentation&lt;/A&gt;&lt;/P&gt;&lt;P&gt;and in &lt;A class="" href="https://www.nxp.com/webapp/Download?colCode=L4.19.35_1.1.0_SCFWKIT-1.2.7.1&amp;amp;appType=license" target="_blank"&gt;SCFW Porting Kit&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 24 Feb 2020 10:06:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-does-the-scu-interact-with-m4-or-Acore/m-p/1003670#M148754</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-02-24T10:06:24Z</dc:date>
    </item>
    <item>
      <title>Re: How does the scu interact with m4 or Acore?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-does-the-scu-interact-with-m4-or-Acore/m-p/1003671#M148755</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hi,igorpadykov&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;First of all, thank you for your quick reply!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;According to the documentation, the scu interacts with m4 primarily through ipc. In the scfw_api,the communication function is found:&lt;/P&gt;&lt;P&gt;1.ipc_read();&lt;/P&gt;&lt;P&gt;2.ipc_write();&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Through these functions, the communication link from m4 to scu can be realized.&amp;nbsp;However, the communication from scu to m4 failed.&amp;nbsp;Can you provide a more detailed example of communication from scu to m4?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR,&lt;/P&gt;&lt;P&gt;liwan special.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Feb 2020 14:07:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-does-the-scu-interact-with-m4-or-Acore/m-p/1003671#M148755</guid>
      <dc:creator>189659318</dc:creator>
      <dc:date>2020-02-25T14:07:38Z</dc:date>
    </item>
    <item>
      <title>Re: How does the scu interact with m4 or Acore?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-does-the-scu-interact-with-m4-or-Acore/m-p/1347548#M180740</link>
      <description>&lt;P&gt;Hope it will be useful to you&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/117572"&gt;@189659318&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;"&lt;SPAN&gt;Now, I want the scu would reply to m4 when it receives the message from m4. Similar logic has not been found in the SDK." - Let's consider a FreeRTOS example for M4 cores:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;IPC uses MU that is bi-directional connections, thus, the protocol that is used always works as a following:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;M4/AP cores : ipc_write(some command)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;SCU ipc_handler:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;-----SCU ipc_read(cmd) - &amp;gt; perform command&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;-----SCU ipc_write(result)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;M4/Ap core result =ipc_read()&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Take a look at&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;SCU platform/svc/misc/rpc_clnt.c :&amp;nbsp;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;sc_misc_set_control it calls&amp;nbsp;&lt;SPAN&gt;sc_call_rpc&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;in SDK nxp&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;NXP SDK devices/MIMX8QM6/scfw_api/main/ipc_imx8qm.c: sc_call_rpc -&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;you will see sequential execution of commands:&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;sc_call_rpc()&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;....&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp;sc_ipc_write&lt;/SPAN&gt;&lt;SPAN&gt;(ipc, msg);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp;sc_ipc_read&lt;/SPAN&gt;&lt;SPAN&gt;(ipc, msg);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Bulat&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Tue, 28 Sep 2021 11:19:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-does-the-scu-interact-with-m4-or-Acore/m-p/1347548#M180740</guid>
      <dc:creator>bulat_a</dc:creator>
      <dc:date>2021-09-28T11:19:48Z</dc:date>
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