<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
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    <title>topic Re: SPI DMA issue for IXM6ULL in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-issue-for-IXM6ULL/m-p/1001163#M148417</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;any update?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 16 Jan 2020 07:05:51 GMT</pubDate>
    <dc:creator>liqi_wu</dc:creator>
    <dc:date>2020-01-16T07:05:51Z</dc:date>
    <item>
      <title>SPI DMA issue for IXM6ULL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-issue-for-IXM6ULL/m-p/1001157#M148411</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;current I use IMX6ULL, I meat a SPI DMA issue.&lt;/P&gt;&lt;P&gt;I configated SPI as&amp;nbsp;POL=0, PHA=1. When I use SPI polling to do data transfer, then it is OK.&lt;/P&gt;&lt;P&gt;But when I use SPI DMA to do data&amp;nbsp;&lt;SPAN&gt;transfer,&amp;nbsp; then the SPI timing look like&amp;nbsp;POL=0, PHA=0.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;what is wrong with it? is there something wrong configuration while in SPI DMA or in SPI DMA, IMX6ULL only support&amp;nbsp;POL=0, PHA=0?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 13 Jan 2020 07:46:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-issue-for-IXM6ULL/m-p/1001157#M148411</guid>
      <dc:creator>liqi_wu</dc:creator>
      <dc:date>2020-01-13T07:46:06Z</dc:date>
    </item>
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      <title>Re: SPI DMA issue for IXM6ULL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-issue-for-IXM6ULL/m-p/1001158#M148412</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi liqi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;what bsp used in the case, please try nxp official bsp from&lt;/P&gt;&lt;P&gt;source.codeaurora.org/external/imx/linux-imx&amp;nbsp; repository&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://source.codeaurora.org/external/imx/linux-imx/tree/?h=imx_4.19.35_1.1.0" title="https://source.codeaurora.org/external/imx/linux-imx/tree/?h=imx_4.19.35_1.1.0"&gt;linux-imx - i.MX Linux kernel&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Documentation&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/design/i.mx-developer-resources/i.mx-software-and-development-tools:IMX-SW" title="https://www.nxp.com/design/i.mx-developer-resources/i.mx-software-and-development-tools:IMX-SW"&gt;i.MX Software and Development Tools | NXP&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Jan 2020 00:48:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-issue-for-IXM6ULL/m-p/1001158#M148412</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-01-14T00:48:12Z</dc:date>
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    <item>
      <title>Re: SPI DMA issue for IXM6ULL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-issue-for-IXM6ULL/m-p/1001159#M148413</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi igorpadykov,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;No use bsp and no use linux. I just use the demo(sdma_b2b_transfer) in&amp;nbsp;SDK_2.2_MCIM6ULL.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Jan 2020 02:22:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-issue-for-IXM6ULL/m-p/1001159#M148413</guid>
      <dc:creator>liqi_wu</dc:creator>
      <dc:date>2020-01-14T02:22:02Z</dc:date>
    </item>
    <item>
      <title>Re: SPI DMA issue for IXM6ULL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-issue-for-IXM6ULL/m-p/1001160#M148414</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi liqi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please try to test on&amp;nbsp;MX6ULL EVK board.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Jan 2020 06:38:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-issue-for-IXM6ULL/m-p/1001160#M148414</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-01-14T06:38:09Z</dc:date>
    </item>
    <item>
      <title>Re: SPI DMA issue for IXM6ULL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-issue-for-IXM6ULL/m-p/1001161#M148415</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi igorpadykov,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I will try it on IMX6ULL EVK board. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope you also can try it if possible.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;发件人: bounces+210748-fda0-liqi_wu=163.com@jiveon.jivesoftware.com  代表 igorpadykov&lt;/P&gt;&lt;P&gt;发送时间: 2020年1月14日 14:39&lt;/P&gt;&lt;P&gt;收件人: liqi wu &amp;lt;liqi_wu@163.com&amp;gt;&lt;/P&gt;&lt;P&gt;主题: Re:  - Re: SPI DMA issue for IXM6ULL&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &amp;lt;https://community.freescale.com/resources/statics/1000/35400-NXP-Community-Email-banner-600x75.jpg&amp;gt; NXP Community &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Re: SPI DMA issue for IXM6ULL &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;reply from igorpadykov &amp;lt;https://community.nxp.com/people/igorpadykov?et=watches.email.thread&amp;gt;  in i.MX Processors - View the full discussion &amp;lt;https://community.nxp.com/message/1254956?commentID=1254956&amp;amp;et=watches.email.thread#comment-1254956&amp;gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Jan 2020 14:27:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-issue-for-IXM6ULL/m-p/1001161#M148415</guid>
      <dc:creator>liqi_wu</dc:creator>
      <dc:date>2020-01-14T14:27:29Z</dc:date>
    </item>
    <item>
      <title>Re: SPI DMA issue for IXM6ULL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-issue-for-IXM6ULL/m-p/1001162#M148416</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi  &amp;lt;https://community.nxp.com/people/igorpadykov?et=watches.email.thread&amp;gt; igorpadykov,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Just as you said, I try it on the IMX6ULL EVK. But the result is same as I said in previously email. The timing is attached.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have you also try it?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;//SPI configuration: baudRate_Bps=20000000     burstLength = 32&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;static void ECSPI_GetDefaultChannelConfig(ecspi_channel_config_t *config)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;{&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;    config-&amp;gt;channelMode = kECSPI_Slave;                              /&lt;STRONG&gt;!&amp;lt; ECSPI peripheral operates in slave mode.&lt;/STRONG&gt;/&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;    config-&amp;gt;clockInactiveState = kECSPI_ClockInactiveStateLow;       /*!&amp;lt; Clock line (SCLK) inactive state */&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;    config-&amp;gt;dataLineInactiveState = kECSPI_DataLineInactiveStateLow; /*!&amp;lt; Data line (MOSI&amp;amp;MISO) inactive state */&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;    config-&amp;gt;chipSlectActiveState = kECSPI_ChipSelectActiveStateLow;  /*!&amp;lt; Chip select(SS) line active state */&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;    config-&amp;gt;waveForm = kECSPI_WaveFormSingle;                        /*!&amp;lt; ECSPI SS wave form */&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;    config-&amp;gt;polarity = kECSPI_PolarityActiveHigh;                    /*!&amp;lt; Clock polarity */&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;    config-&amp;gt;phase = kECSPI_ClockPhaseSecondEdge;                      /*!&amp;lt; clock phase */&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;wuliqi&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;发件人: bounces+210748-fda0-liqi_wu=163.com@jiveon.jivesoftware.com  代表 igorpadykov&lt;/P&gt;&lt;P&gt;发送时间: 2020年1月14日 14:39&lt;/P&gt;&lt;P&gt;收件人: liqi wu &amp;lt;liqi_wu@163.com&amp;gt;&lt;/P&gt;&lt;P&gt;主题: Re:  - Re: SPI DMA issue for IXM6ULL&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &amp;lt;https://community.freescale.com/resources/statics/1000/35400-NXP-Community-Email-banner-600x75.jpg&amp;gt; NXP Community &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Re: SPI DMA issue for IXM6ULL &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;reply from igorpadykov &amp;lt;https://community.nxp.com/people/igorpadykov?et=watches.email.thread&amp;gt;  in i.MX Processors - View the full discussion &amp;lt;https://community.nxp.com/message/1254956?commentID=1254956&amp;amp;et=watches.email.thread#comment-1254956&amp;gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jan 2020 06:20:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-issue-for-IXM6ULL/m-p/1001162#M148416</guid>
      <dc:creator>liqi_wu</dc:creator>
      <dc:date>2020-01-15T06:20:40Z</dc:date>
    </item>
    <item>
      <title>Re: SPI DMA issue for IXM6ULL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-issue-for-IXM6ULL/m-p/1001163#M148417</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;any update?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 16 Jan 2020 07:05:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-issue-for-IXM6ULL/m-p/1001163#M148417</guid>
      <dc:creator>liqi_wu</dc:creator>
      <dc:date>2020-01-16T07:05:51Z</dc:date>
    </item>
    <item>
      <title>Re: SPI DMA issue for IXM6ULL</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-issue-for-IXM6ULL/m-p/1001164#M148418</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;SPAN style="background-color: #ffffff; color: #646464; font-size: 18.004px; "&gt;igorpadykov,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="background-color: #ffffff; color: #646464; font-size: 18.004px; "&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="background-color: #ffffff; color: #646464; font-size: 18.004px; "&gt;any update for this case? or have you try it on&amp;nbsp;&lt;SPAN style="color: #51626f;"&gt;IMX6ULL EVK board?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 17 Jan 2020 01:55:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-issue-for-IXM6ULL/m-p/1001164#M148418</guid>
      <dc:creator>liqi_wu</dc:creator>
      <dc:date>2020-01-17T01:55:13Z</dc:date>
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</rss>

