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    <title>topic i.MX6ULL NAND boot question in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-NAND-boot-question/m-p/998915#M148152</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;1. In the Table 8-10 of i.MX6ULL reference manual &amp;lt;http://nxp.com/doc/imx6ullrm&amp;gt;, BOOT_CFG2[4:3] for boot search count. Are 00, 01 both for two boot search count?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/102660i7FFE3574D2326CEB/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;2.&amp;nbsp;&lt;SPAN&gt;In the Table 5-7&amp;nbsp;of i.MX6ULL reference manual &amp;lt;http://nxp.com/doc/imx6ullrm&amp;gt;, there are some reserved pins for NAND boot, like BOOT_CFG2[0]. What is the recommended status for these reserved&amp;nbsp;pins when booting? NC, pull-up, pull-down?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/102704i83A763E7E1339F33/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 21 Feb 2020 01:28:00 GMT</pubDate>
    <dc:creator>m_c</dc:creator>
    <dc:date>2020-02-21T01:28:00Z</dc:date>
    <item>
      <title>i.MX6ULL NAND boot question</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-NAND-boot-question/m-p/998915#M148152</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;1. In the Table 8-10 of i.MX6ULL reference manual &amp;lt;http://nxp.com/doc/imx6ullrm&amp;gt;, BOOT_CFG2[4:3] for boot search count. Are 00, 01 both for two boot search count?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/102660i7FFE3574D2326CEB/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;2.&amp;nbsp;&lt;SPAN&gt;In the Table 5-7&amp;nbsp;of i.MX6ULL reference manual &amp;lt;http://nxp.com/doc/imx6ullrm&amp;gt;, there are some reserved pins for NAND boot, like BOOT_CFG2[0]. What is the recommended status for these reserved&amp;nbsp;pins when booting? NC, pull-up, pull-down?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/102704i83A763E7E1339F33/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 21 Feb 2020 01:28:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-NAND-boot-question/m-p/998915#M148152</guid>
      <dc:creator>m_c</dc:creator>
      <dc:date>2020-02-21T01:28:00Z</dc:date>
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    <item>
      <title>Re: i.MX6ULL NAND boot question</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-NAND-boot-question/m-p/998916#M148153</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;1.- Yes, you're a correct&lt;/P&gt;&lt;P&gt;2.- You may place a pull-down resistor to this reserved pins, if planning to use fuses please do not burn these, as the behavior may be unpredictable.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hope this helps,&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Aldo.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Feb 2020 17:15:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-NAND-boot-question/m-p/998916#M148153</guid>
      <dc:creator>AldoG</dc:creator>
      <dc:date>2020-02-26T17:15:36Z</dc:date>
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