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    <title>i.MX ProcessorsのトピックRe: How to set vsync-len for MIPI-DSI Host?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/How-to-set-vsync-len-for-MIPI-DSI-Host/m-p/998635#M148093</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;yes, dsi bridge doesn't set this in the dts file, depends on what panel you use, you can add this in the dts file according to the panel you use&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 27 Feb 2020 07:41:20 GMT</pubDate>
    <dc:creator>joanxie</dc:creator>
    <dc:date>2020-02-27T07:41:20Z</dc:date>
    <item>
      <title>How to set vsync-len for MIPI-DSI Host?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-set-vsync-len-for-MIPI-DSI-Host/m-p/998632#M148090</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello all&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does anyone know how to set DSI vsync-len&amp;nbsp;value on IMX8MQ?&lt;/P&gt;&lt;P&gt;I've looked at chapter 13.6 in IMX8MQ Reference Manual (&lt;SPAN class=""&gt;IMX8MDQLQRM&lt;/SPAN&gt;), it seems only hsync-len can be set by&amp;nbsp; &lt;SPAN class=""&gt;MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA&lt;/SPAN&gt;&amp;nbsp;register.&lt;/P&gt;&lt;P&gt;However, these MIPI-DSI parameters (hsync len, vsync len) can be found in IMX8MM reference manual ( &lt;SPAN class=""&gt;13.5.5.1.13)&lt;/SPAN&gt;.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 07 Feb 2020 05:18:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-set-vsync-len-for-MIPI-DSI-Host/m-p/998632#M148090</guid>
      <dc:creator>huynhduchau</dc:creator>
      <dc:date>2020-02-07T05:18:58Z</dc:date>
    </item>
    <item>
      <title>Re: How to set vsync-len for MIPI-DSI Host?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-set-vsync-len-for-MIPI-DSI-Host/m-p/998633#M148091</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;you can set this in the dts file, for example：rm67191&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;display-timings {&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;timing {&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;clock-frequency = &amp;lt;132000000&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;hactive = &amp;lt;1080&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;vactive = &amp;lt;1920&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;hfront-porch = &amp;lt;20&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;hsync-len = &amp;lt;2&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;hback-porch = &amp;lt;34&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;vfront-porch = &amp;lt;10&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;vsync-len = &amp;lt;5&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;vback-porch = &amp;lt;4&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;hsync-active = &amp;lt;0&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;vsync-active = &amp;lt;0&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;de-active = &amp;lt;0&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;pixelclk-active = &amp;lt;0&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;};&lt;BR /&gt;&amp;nbsp;&amp;nbsp;};&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Feb 2020 07:19:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-set-vsync-len-for-MIPI-DSI-Host/m-p/998633#M148091</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2020-02-11T07:19:01Z</dc:date>
    </item>
    <item>
      <title>Re: How to set vsync-len for MIPI-DSI Host?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-set-vsync-len-for-MIPI-DSI-Host/m-p/998634#M148092</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks for hint.&lt;/P&gt;&lt;P&gt;But I believe&amp;nbsp;vsync-len value won't be set to MIPI-DSI bridge.&lt;/P&gt;&lt;P&gt;Kernel driver&amp;nbsp;lacks of setting vsync-len as I read from this code:&lt;/P&gt;&lt;P&gt;static void nwl_dsi_config_dpi(struct nwl_mipi_dsi *dsi)&lt;BR /&gt;{&lt;BR /&gt; struct device *dev = dsi-&amp;gt;dev;&lt;BR /&gt; struct mipi_dsi_device *dsi_device = dsi-&amp;gt;dsi_device;&lt;BR /&gt; struct videomode vm;&lt;BR /&gt; enum dpi_pixel_format pixel_format =&lt;BR /&gt; nwl_dsi_get_dpi_pixel_format(dsi_device-&amp;gt;format);&lt;BR /&gt; enum dpi_interface_color_coding color_coding =&lt;BR /&gt; nwl_dsi_get_dpi_interface_color_coding(dsi_device-&amp;gt;format);&lt;BR /&gt; bool burst_mode;&lt;/P&gt;&lt;P&gt;drm_display_mode_to_videomode(dsi-&amp;gt;curr_mode, &amp;amp;vm);&lt;/P&gt;&lt;P&gt;nwl_dsi_write(dsi, INTERFACE_COLOR_CODING, color_coding);&lt;BR /&gt; nwl_dsi_write(dsi, PIXEL_FORMAT, pixel_format);&lt;BR /&gt; DRM_DEV_DEBUG_DRIVER(dev, "DSI format is: %d (CC=%d, PF=%d)\n",&lt;BR /&gt; dsi_device-&amp;gt;format, color_coding, pixel_format);&lt;/P&gt;&lt;P&gt;/*TODO: need to make polarity configurable */&lt;BR /&gt; nwl_dsi_write(dsi, VSYNC_POLARITY, 0x00);&lt;BR /&gt; nwl_dsi_write(dsi, HSYNC_POLARITY, 0x00);&lt;/P&gt;&lt;P&gt;burst_mode = (dsi_device-&amp;gt;mode_flags &amp;amp; MIPI_DSI_MODE_VIDEO_BURST) &amp;amp;&amp;amp;&lt;BR /&gt; !(dsi_device-&amp;gt;mode_flags &amp;amp; MIPI_DSI_MODE_VIDEO_SYNC_PULSE);&lt;/P&gt;&lt;P&gt;if (burst_mode) {&lt;BR /&gt; nwl_dsi_write(dsi, VIDEO_MODE, 0x2);&lt;BR /&gt; nwl_dsi_write(dsi, PIXEL_FIFO_SEND_LEVEL, 256);&lt;BR /&gt; } else {&lt;BR /&gt; nwl_dsi_write(dsi, VIDEO_MODE, 0x0);&lt;BR /&gt; nwl_dsi_write(dsi, PIXEL_FIFO_SEND_LEVEL, vm.hactive);&lt;BR /&gt; }&lt;/P&gt;&lt;P&gt;nwl_dsi_write(dsi, HFP, vm.hfront_porch);&lt;BR /&gt; nwl_dsi_write(dsi, HBP, vm.hback_porch);&lt;BR /&gt; nwl_dsi_write(dsi, HSA, vm.hsync_len);&lt;/P&gt;&lt;P&gt;nwl_dsi_write(dsi, ENABLE_MULT_PKTS, 0x0);&lt;BR /&gt; nwl_dsi_write(dsi, BLLP_MODE, 0x1);&lt;BR /&gt; nwl_dsi_write(dsi, ENABLE_MULT_PKTS, 0x0);&lt;BR /&gt; nwl_dsi_write(dsi, USE_NULL_PKT_BLLP, 0x0);&lt;BR /&gt; nwl_dsi_write(dsi, VC, 0x0);&lt;/P&gt;&lt;P&gt;nwl_dsi_write(dsi, PIXEL_PAYLOAD_SIZE, vm.hactive);&lt;BR /&gt; nwl_dsi_write(dsi, VACTIVE, vm.vactive);&lt;BR /&gt; nwl_dsi_write(dsi, VBP, vm.vback_porch);&lt;BR /&gt; nwl_dsi_write(dsi, VFP, vm.vfront_porch);&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Btw, I'm using LCDIF as source for the bridge, and LCDIF register values seem correct.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 12 Feb 2020 08:04:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-set-vsync-len-for-MIPI-DSI-Host/m-p/998634#M148092</guid>
      <dc:creator>huynhduchau</dc:creator>
      <dc:date>2020-02-12T08:04:48Z</dc:date>
    </item>
    <item>
      <title>Re: How to set vsync-len for MIPI-DSI Host?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-to-set-vsync-len-for-MIPI-DSI-Host/m-p/998635#M148093</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;yes, dsi bridge doesn't set this in the dts file, depends on what panel you use, you can add this in the dts file according to the panel you use&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 27 Feb 2020 07:41:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-to-set-vsync-len-for-MIPI-DSI-Host/m-p/998635#M148093</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2020-02-27T07:41:20Z</dc:date>
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