i.MX ProcessorsのトピックGPIO setup changes

GPIO setup changes

glenfine — Tue, 17 Dec 2019 21:37:02 GMT

Hi,

This has probably been answered before. We have an i.MX6D where we have to invert a GPIO polarity on bootup.

Currently it has a direction of 'in' (direction) and a value of '1'. We need it to, by default, have a value of '0'.

Changing the direction probably won't be needed until later when we need to toggle the value at runtime.

We have to do this at the time the bootloader (u-boot) initializes the processor. Doing this via the OS is not an option.

In imx6q-pinfunc.h should I change the input_val from 0x0 to 0x1

#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11          0x1b4 0x4c8 0x000 0x5 0x0

And is there anything I have to change in the dts file? (like 0x80000000 to 0xC0000000)

MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x80000000

Regards,

Glen

Re: GPIO setup changes

igorpadykov — Wed, 18 Dec 2019 10:54:29 GMT

Hi Glen

in dts file can be changed pad settings as for example described in

sect.36.4.383 Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO05)

i.MX 6Dual/6Quad Applications Processor Reference Manual

Other settings should be done in uboot sources.

Best regards
igor
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Re: GPIO setup changes

glenfine — Wed, 18 Dec 2019 19:38:37 GMT

Thank you Igor. But this is confusing. I find no entry for IOMUXC_SW_PAD_CTL_PAD_GPIO05 in my dts.

There is only

MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x80000000

in the 'hog' section of the dts.

Basically what we need is the value for GPI5, Pin 11 to be the opposite of what it is by default. It is currently HIGH (a '1') and I need it to be LOW ('0') at boot time or the alarm hooked to the CPLD will be blaring.

Am I misunderstanding what IOMUXC_SW_PAD_CTL_PAD_GPIO05 represents? or how to apply it? I see the write up in the RM but that doesn't tell me anything. From what I understand is that the IOMUXC will only control things like drive strength and pullup/pulldown. How does this apply to a single pin?

Cheers,

Glen

Re: GPIO setup changes

igorpadykov — Thu, 19 Dec 2019 00:50:22 GMT

Hi Glen

for MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 it is necessary to look at IOMUX DISP0_DAT17 description :

sect.36.4.302 Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17)

>From what I understand is that the IOMUXC will only control things like drive strength

>and pullup/pulldown. How does this apply to a single pin?

right.

Best regards
igor