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  <channel>
    <title>topic Re: IRQ handler for iMX8 SCU GPIO in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IRQ-handler-for-iMX8-SCU-GPIO/m-p/990662#M147047</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Take&amp;nbsp;arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts as a reference.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;For the PCI node we have:&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;amp;pcieb{&lt;BR /&gt; ext_osc = &amp;lt;1&amp;gt;;&lt;BR /&gt; pinctrl-names = "default";&lt;BR /&gt; pinctrl-0 = &amp;lt;&amp;amp;pinctrl_pcieb&amp;gt;;&lt;BR /&gt; clkreq-gpio = &amp;lt;&amp;amp;gpio4 1 GPIO_ACTIVE_LOW&amp;gt;;&lt;BR /&gt; disable-gpio = &amp;lt;&amp;amp;pca9557_a 2 GPIO_ACTIVE_LOW&amp;gt;;&lt;BR /&gt; reset-gpio = &amp;lt;&amp;amp;gpio4 0 GPIO_ACTIVE_LOW&amp;gt;;&lt;BR /&gt; epdev_on-supply = &amp;lt;&amp;amp;epdev_on&amp;gt;;&lt;BR /&gt; status = "okay";&lt;BR /&gt;};&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;pinctrl_pcieb defines the GPIOs used to control PCI and are defined like:&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt; pinctrl_pcieb: pcieagrp{&lt;BR /&gt; fsl,pins = &amp;lt;&lt;BR /&gt; SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021&lt;BR /&gt; SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021&lt;BR /&gt; SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x06000021&lt;BR /&gt; &amp;gt;;&lt;BR /&gt; };&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Is this the kind of example that you are looking for?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 14 Jan 2020 09:14:12 GMT</pubDate>
    <dc:creator>jimmychan</dc:creator>
    <dc:date>2020-01-14T09:14:12Z</dc:date>
    <item>
      <title>IRQ handler for iMX8 SCU GPIO</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IRQ-handler-for-iMX8-SCU-GPIO/m-p/990657#M147042</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The SCU SCFW porting kit provides different APIs.&lt;/P&gt;&lt;P&gt;I would like to enable interrupt&amp;nbsp;on GPIO in the SCU firmware ( SCFW).&lt;/P&gt;&lt;P&gt;The board init of iMX8QM MEK uses&amp;nbsp;FGPIO_PinInit to handle SCU GPIO.&lt;/P&gt;&lt;P&gt;The driver library has&amp;nbsp;FGPIO_ClearPinsInterruptFlags to clean the interrupt.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;How to I enable the interrupt ?&lt;/P&gt;&lt;P&gt;The documentation has the following example, but the function to set interrupt is not there. Which IRQ would correspond ?&lt;/P&gt;&lt;P&gt;```&lt;/P&gt;&lt;P&gt;PORT_SetPinInterruptConfig(BOARD_SW2_PORT, BOARD_SW2_FGPIO_PIN, kPORT_InterruptFallingEdge);&lt;BR /&gt;NVIC_EnableIRQ(BOARD_SW2_IRQ);&lt;/P&gt;&lt;P&gt;```&lt;/P&gt;&lt;P&gt;Would this functionality be handled via the SVC service of the SCFW ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If interrupt are not available on SCU GPIO, how would I used IGPIO driver interrupt? how the IRQ is process for those GPIO ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;BR /&gt;Stan&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 17 Dec 2019 14:03:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IRQ-handler-for-iMX8-SCU-GPIO/m-p/990657#M147042</guid>
      <dc:creator>sbertrand</dc:creator>
      <dc:date>2019-12-17T14:03:14Z</dc:date>
    </item>
    <item>
      <title>Re: IRQ handler for iMX8 SCU GPIO</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IRQ-handler-for-iMX8-SCU-GPIO/m-p/990658#M147043</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Could you tell me which version of BSP are you using?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 24 Dec 2019 06:47:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IRQ-handler-for-iMX8-SCU-GPIO/m-p/990658#M147043</guid>
      <dc:creator>jimmychan</dc:creator>
      <dc:date>2019-12-24T06:47:49Z</dc:date>
    </item>
    <item>
      <title>Re: IRQ handler for iMX8 SCU GPIO</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IRQ-handler-for-iMX8-SCU-GPIO/m-p/990659#M147044</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am using the SCFW porting kit 1.2.9 version for scfw_export_mx8qm_b0 :&amp;nbsp;imx-scfw-porting-kit-1.2.9&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 06 Jan 2020 08:22:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IRQ-handler-for-iMX8-SCU-GPIO/m-p/990659#M147044</guid>
      <dc:creator>sbertrand</dc:creator>
      <dc:date>2020-01-06T08:22:44Z</dc:date>
    </item>
    <item>
      <title>Re: IRQ handler for iMX8 SCU GPIO</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IRQ-handler-for-iMX8-SCU-GPIO/m-p/990660#M147045</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Are you using the L4.19.35_1.1.0?&lt;/P&gt;&lt;P&gt;The SCFWKIT is 1.2.7.1&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com/webapp/sps/download/license.jsp?colCode=L4.19.35_1.1.0_SCFWKIT-1.2.7.1&amp;amp;appType=file1&amp;amp;DOWNLOAD_ID=null"&gt;https://www.nxp.com/webapp/sps/download/license.jsp?colCode=L4.19.35_1.1.0_SCFWKIT-1.2.7.1&amp;amp;appType=file1&amp;amp;DOWNLOAD_ID=null&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 07 Jan 2020 12:58:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IRQ-handler-for-iMX8-SCU-GPIO/m-p/990660#M147045</guid>
      <dc:creator>jimmychan</dc:creator>
      <dc:date>2020-01-07T12:58:14Z</dc:date>
    </item>
    <item>
      <title>Re: IRQ handler for iMX8 SCU GPIO</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IRQ-handler-for-iMX8-SCU-GPIO/m-p/990661#M147046</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Does the 1.2.7.1 has SCU GPIO interrupt support ?&lt;/P&gt;&lt;P&gt;Which IRQ routine handles the GPIO interrupt ?&lt;/P&gt;&lt;P&gt;Is there a user function available to&amp;nbsp;add custom handling for GPIO interrupt ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;BR /&gt;Stan&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 07 Jan 2020 13:14:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IRQ-handler-for-iMX8-SCU-GPIO/m-p/990661#M147046</guid>
      <dc:creator>sbertrand</dc:creator>
      <dc:date>2020-01-07T13:14:06Z</dc:date>
    </item>
    <item>
      <title>Re: IRQ handler for iMX8 SCU GPIO</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IRQ-handler-for-iMX8-SCU-GPIO/m-p/990662#M147047</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Take&amp;nbsp;arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts as a reference.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;For the PCI node we have:&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;amp;pcieb{&lt;BR /&gt; ext_osc = &amp;lt;1&amp;gt;;&lt;BR /&gt; pinctrl-names = "default";&lt;BR /&gt; pinctrl-0 = &amp;lt;&amp;amp;pinctrl_pcieb&amp;gt;;&lt;BR /&gt; clkreq-gpio = &amp;lt;&amp;amp;gpio4 1 GPIO_ACTIVE_LOW&amp;gt;;&lt;BR /&gt; disable-gpio = &amp;lt;&amp;amp;pca9557_a 2 GPIO_ACTIVE_LOW&amp;gt;;&lt;BR /&gt; reset-gpio = &amp;lt;&amp;amp;gpio4 0 GPIO_ACTIVE_LOW&amp;gt;;&lt;BR /&gt; epdev_on-supply = &amp;lt;&amp;amp;epdev_on&amp;gt;;&lt;BR /&gt; status = "okay";&lt;BR /&gt;};&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;pinctrl_pcieb defines the GPIOs used to control PCI and are defined like:&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt; pinctrl_pcieb: pcieagrp{&lt;BR /&gt; fsl,pins = &amp;lt;&lt;BR /&gt; SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021&lt;BR /&gt; SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021&lt;BR /&gt; SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x06000021&lt;BR /&gt; &amp;gt;;&lt;BR /&gt; };&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Is this the kind of example that you are looking for?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Jan 2020 09:14:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IRQ-handler-for-iMX8-SCU-GPIO/m-p/990662#M147047</guid>
      <dc:creator>jimmychan</dc:creator>
      <dc:date>2020-01-14T09:14:12Z</dc:date>
    </item>
    <item>
      <title>Re: IRQ handler for iMX8 SCU GPIO</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IRQ-handler-for-iMX8-SCU-GPIO/m-p/990663#M147048</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This is not what I am looking for.&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am looking for SCU firmware bare metal code to support native SCU gpio block interrupt.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The device tree is not helpful with the bare metal code for the SCU firmware.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Stan&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Jan 2020 09:19:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IRQ-handler-for-iMX8-SCU-GPIO/m-p/990663#M147048</guid>
      <dc:creator>sbertrand</dc:creator>
      <dc:date>2020-01-14T09:19:08Z</dc:date>
    </item>
    <item>
      <title>Re: IRQ handler for iMX8 SCU GPIO</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IRQ-handler-for-iMX8-SCU-GPIO/m-p/990664#M147049</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The Rapid GPIO on the SCU do not support interrupt as mentioned for the M4 complex :&amp;nbsp;&lt;A href="https://community.nxp.com/thread/523693"&gt;https://community.nxp.com/thread/523693&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 06 Feb 2020 08:45:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IRQ-handler-for-iMX8-SCU-GPIO/m-p/990664#M147049</guid>
      <dc:creator>sbertrand</dc:creator>
      <dc:date>2020-02-06T08:45:24Z</dc:date>
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