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    <title>topic Re: SABRE Board for Smart Devices in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/SABRE-Board-for-Smart-Devices/m-p/221727#M14702</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; The i.MX6 MMDC supports DDR data bus width of x16, x32 or x64 bits.&lt;BR /&gt; On the SABRE Board for Smart Devices x64 configuration is applied.&lt;BR /&gt; Generally it is possible&amp;nbsp; to use only one DDR part (D[0-15]) or two&lt;BR /&gt; parts (D[0-31]). DDR initialization should be changes to reflect &lt;BR /&gt; bus size in&amp;nbsp; MDCTL[DSIZ].&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 11 Jan 2013 04:44:43 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2013-01-11T04:44:43Z</dc:date>
    <item>
      <title>SABRE Board for Smart Devices</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SABRE-Board-for-Smart-Devices/m-p/221726#M14701</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;In the reference SABRE Board for Smart Devices, there is a provision for 1GB with 4 chips. Is it possible to only populate 2 of those for a total of 512MB? Would that work or do some changes need to be made in the schematics?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Also, it looks like the dual lite will work with no changes to the board schematics?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for any help or pointers.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;RS&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 08 Jan 2013 04:19:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SABRE-Board-for-Smart-Devices/m-p/221726#M14701</guid>
      <dc:creator>rs1932</dc:creator>
      <dc:date>2013-01-08T04:19:34Z</dc:date>
    </item>
    <item>
      <title>Re: SABRE Board for Smart Devices</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SABRE-Board-for-Smart-Devices/m-p/221727#M14702</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="font-family: 'Verdana','sans-serif';"&gt;&amp;nbsp; The i.MX6 MMDC supports DDR data bus width of x16, x32 or x64 bits.&lt;BR /&gt; On the SABRE Board for Smart Devices x64 configuration is applied.&lt;BR /&gt; Generally it is possible&amp;nbsp; to use only one DDR part (D[0-15]) or two&lt;BR /&gt; parts (D[0-31]). DDR initialization should be changes to reflect &lt;BR /&gt; bus size in&amp;nbsp; MDCTL[DSIZ].&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 11 Jan 2013 04:44:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SABRE-Board-for-Smart-Devices/m-p/221727#M14702</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2013-01-11T04:44:43Z</dc:date>
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