<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic PMIC for i.MX8QXP in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/PMIC-for-i-MX8QXP/m-p/983856#M146166</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am referring to i.MX 8QXP MEK schematics in which they have employed 'PC33PF8100CCES' PMIC to power the i.MX 8QXP processor. In this regard can you please confirm the following:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1) I couldn't find 'PC33PF8100CCES' part on NXP website. Instead there are equivalent parts MC33PF8100FJES/MC33PF8200DEES. Are these the replacement parts for the 'PC33PF8100CCES'? Can you also please confirm the difference between 'PC33PF8100CCES' and its equivalent parts.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2) SW3 and SW4 channels of PMIC 'PC33PF8100CCES' in i.MX 8QXP MEK schematics are powering the VCC_GPU and VCC_CPU respectively. If MC33PF8100FJES/MC33PF8200DEES are replacement parts then SW3 and SW4 of new parts cannot be used to power VCC_GPU and VCC_CPU because the OTP configuration reports for these ICs mention that SW3 and SW4 are disabled. Can you please help us in understanding this conflict/ambiguity?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Shyam&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 04 Mar 2020 07:17:48 GMT</pubDate>
    <dc:creator>shyam_j</dc:creator>
    <dc:date>2020-03-04T07:17:48Z</dc:date>
    <item>
      <title>PMIC for i.MX8QXP</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PMIC-for-i-MX8QXP/m-p/983856#M146166</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am referring to i.MX 8QXP MEK schematics in which they have employed 'PC33PF8100CCES' PMIC to power the i.MX 8QXP processor. In this regard can you please confirm the following:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1) I couldn't find 'PC33PF8100CCES' part on NXP website. Instead there are equivalent parts MC33PF8100FJES/MC33PF8200DEES. Are these the replacement parts for the 'PC33PF8100CCES'? Can you also please confirm the difference between 'PC33PF8100CCES' and its equivalent parts.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2) SW3 and SW4 channels of PMIC 'PC33PF8100CCES' in i.MX 8QXP MEK schematics are powering the VCC_GPU and VCC_CPU respectively. If MC33PF8100FJES/MC33PF8200DEES are replacement parts then SW3 and SW4 of new parts cannot be used to power VCC_GPU and VCC_CPU because the OTP configuration reports for these ICs mention that SW3 and SW4 are disabled. Can you please help us in understanding this conflict/ambiguity?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Shyam&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 04 Mar 2020 07:17:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PMIC-for-i-MX8QXP/m-p/983856#M146166</guid>
      <dc:creator>shyam_j</dc:creator>
      <dc:date>2020-03-04T07:17:48Z</dc:date>
    </item>
    <item>
      <title>Re: PMIC for i.MX8QXP</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PMIC-for-i-MX8QXP/m-p/983857#M146167</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Shyam&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;differencies are described in datasheet&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/data-sheet/PF8100_PF8200.pdf" title="https://www.nxp.com/docs/en/data-sheet/PF8100_PF8200.pdf"&gt;https://www.nxp.com/docs/en/data-sheet/PF8100_PF8200.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;MC33PF8100FJES is replacement part for the 'PC33PF8100CCES'.&lt;/P&gt;&lt;P&gt;SW3,4 are disabled for power-up sequence and can be enabled by software&lt;/P&gt;&lt;P&gt;after processor powered up. Note in i.MX8QXP/QM SCU (M4) module is&lt;/P&gt;&lt;P&gt;used for initial starting up of processor.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 04 Mar 2020 23:20:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PMIC-for-i-MX8QXP/m-p/983857#M146167</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-03-04T23:20:21Z</dc:date>
    </item>
    <item>
      <title>Re: PMIC for i.MX8QXP</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PMIC-for-i-MX8QXP/m-p/983858#M146168</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/igorpadykov"&gt;igorpadykov&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" lang="en"&gt;&lt;SPAN class="" title=""&gt; Hi igor&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="" lang="en"&gt;&lt;SPAN class="" title=""&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class="" lang="en"&gt;&lt;SPAN class="" title=""&gt;Before the system is downloaded, does M4 automatically turn on SW3 and SW4 after power on? If not,how to control M4 to enable SW3 and SW4 ?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;Cheers&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 17 Mar 2020 02:45:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PMIC-for-i-MX8QXP/m-p/983858#M146168</guid>
      <dc:creator>月泉飞星</dc:creator>
      <dc:date>2020-03-17T02:45:29Z</dc:date>
    </item>
    <item>
      <title>Re: PMIC for i.MX8QXP</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PMIC-for-i-MX8QXP/m-p/1381985#M184021</link>
      <description>&lt;P&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;Hi igor&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;Before the system is downloaded, does M4 automatically turn on SW3 and SW4 after power on? If not,how to control M4 to enable SW3 and SW4 ?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 06 Dec 2021 13:06:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PMIC-for-i-MX8QXP/m-p/1381985#M184021</guid>
      <dc:creator>Shivam1</dc:creator>
      <dc:date>2021-12-06T13:06:58Z</dc:date>
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  </channel>
</rss>

