IPU csi0 test

zhiyuan_song — Thu, 28 Nov 2019 04:13:49 GMT

hi，I have a problem. I use the ipucsi test pattern，set csi0 test control register

csi->smfc->idmac

first: idmac configuration

void ipu_general_idmac_config()
{
uint32_t channel = 0;

/* enable channel 0 */
ipu_idmac_channel_enable(channel, 0);

memset((void *)ipu_cpmem_addr(channel), 0, sizeof(ipu_cpmem_t));

    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 1, 0, 29, 0x07000000);
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 1, 29, 29, 0);
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 0, 125, 13, 0x0000027f);
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 0, 138, 12, 0x000001df);

/*setup default pixel format */
ipu_cpmem_set_field(ipu_cpmem_addr(channel), 1, 85, 4, INTERLEAVED_RGB565);

    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 0, 107, 3, 3);
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 1, 116, 3, 5 - 1);
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 1, 119, 3, 6 - 1);
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 1, 122, 3, 5 - 1);
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 1, 125, 3, 0 - 1);
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 1, 128, 5, 0);
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 1, 133, 5, 5);
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 1, 138, 5, 11);
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 1, 143, 5, 16);

ipu_cpmem_set_field(ipu_cpmem_addr(channel), 1, 102, 14, 640 - 1);

    /*setup pixel per burst */
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 1, 78, 7, 15);
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 0, 113, 1, 0);
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 1, 58, 20, 0);

    //setup rotate/vf/hf and block mode
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 0, 119, 1, 0);
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 0, 121, 1, 0);
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 0, 120, 1, 0);
    ipu_cpmem_set_field(ipu_cpmem_addr(channel), 0, 117, 2, 0);

ipu_idmac_channel_mode_sel(channel, 0);

ipu_idmac_channel_enable1(channel, 1);
}

Then, SMFC configuration:

uint32_t ipu_smfc_fifo_allocate(uint32_t channel, uint32_t map,
                                uint32_t burst_size)
{
    switch (channel) {
    case 0:
        writel(map, 0x2650000);//smfc map
        writel(burst_size, 0x2650008);//smfc bs
        break;

    case 1:
        writel(map, 0x2650000);
        writel(burst_size, 0x2650008);
        break;

    case 2:
        writel(map, 0x2650000);
        writel(burst_size, 0x2650008);
        break;

    case 3:
        writel(map, 0x2650000);
        writel(burst_size, 0x2650008);
        break;

    default:
        printf("Wrong channel selected!!\n");
        return -1;
    }

writel(1 << 8, 0x2600000);//enable smfc
return 0;
}

and the csi configuration :

void ipu_csi_config()
{
//test
writel(1 << 24, 0x2630010);//enable test

//writel((readl(0x2600000) | 1 << 28), 0x2600000);//mipi

//writel(0x1e, 0x2638020);//di

writel(((0 << 31) | (1 << 15) | (0 << 3) | (0 << 2) | (0x4 << 24) | (1 << 4) | (0x9f << 16)), 0x2630000);
//writel(((0x04 << 24) | (0x00 << 4) | (0x0 << 16) | (0x1 << 11) | (0x0 << 7) | (0x02 << 8)), 0x2630000);

writel(((0x01df << 16) | (0x027f << 0)), 0x2630004);

writel((readl(0x2600000) | (1 << 0)), 0x2600000);//enable csi0
}

void ipu_buffer()
{
writel(readl(0x26000e4) | (0 << 28), 0x26000e4);
writel(readl(0x2600268) | 1, 0x2600268);

writel(readl(0x26000e4) | (0 << 30), 0x26000e4);
writel(readl(0x2600270) | 1, 0x2600270);
}

void ipu_capture_setup(uint32_t ipu_index, uint32_t csi_interface, uint32_t raw_width,
uint32_t raw_height, uint32_t act_width, uint32_t act_height)
{
uint32_t csi_mem0 = 0x40000000, csi_mem1 = 0;
int32_t csi_pixel_format = NON_INTERLEAVED_YUV420;

    if (csi_interface == CSI_TEST_MODE)
        csi_pixel_format = INTERLEAVED_RGB565;
    // put csi captured image into memory first
    ipu_general_idmac_config();
    /*step2: allocate smfc fifo for CSI input channel */
    ipu_smfc_fifo_allocate(0, 0, 3);
    /*step3: config csi for IPU */
    ipu_csi_config();

memset((void *)csi_mem0, 0xFF, 640 * 480 * 2);
ipu_buffer();
}

My test function is as follows:

int32_t csi_test_mode()
{
int32_t ipu_index = 1, count = 0;
int32_t width = 640, height = 480;

/*step 2: setup IPU: from csi to display */
ipu1_iomux_config();
ipu_sw_reset(ipu_index, 1000);

ipu_capture_setup(ipu_index, CSI_TEST_MODE, width, height, width, height);
while(1){
ipu_csi_test_mode_color(ipu_index, (count++) % 8);
}
}

Why can't I get the generated checkerboard image?

I looked at the memory at 0x08000000 and 0x40000000,I find that the data is constant.0x40000000 looks random

0x08000000 looks regular.data:0x38613860 0x38653864 0x38693868 0x386d386c...

Can you help me?

Re: IPU csi0 test

igorpadykov — Thu, 28 Nov 2019 23:49:03 GMT

Hi song

for ipu csi test pattern example one can check function ipu_csi_test_mode() in

rt-thread/ipu_csi.c at master · RT-Thread/rt-thread · GitHub

Best regards
igor
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Re: IPU csi0 test

zhiyuan_song — Fri, 29 Nov 2019 07:30:15 GMT

hi，igorpadykov,IPU channel 0 interrupt flag bit has become one, how to reset it?

topic IPU csi0 test in i.MX Processors

IPU csi0 test

Re: IPU csi0 test

Re: IPU csi0 test