<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic IMX6UL Linux/OPTEE Increasing RAM in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Linux-OPTEE-Increasing-RAM/m-p/982067#M145935</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm trying to get my board to recognise all my RAM, I had it recognising 128MB but I have 1GB installed. I have used the DDR configuration tool to configure uboot to configure the memory registers and it recognises the full amount of RAM. I can load an image onto the board using UUU, but on a restart I get the message "Starting kernel ..." from uBoot, then a few messages from OP-TEE starting, then the whole system hangs. From booting without my mods, I'd expect to get "Booting Linux on physical CPU 0x0". I have also CFG_DDR_SIZE in OP-TEE to 0x40000000.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What else do I need to configure?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Here is my memory configuration in uboot:&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;//=============================================================================&amp;nbsp; &amp;nbsp;&lt;BR /&gt;// Calibration setup.&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//=============================================================================&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0800 0xA1390003 // DDR_PHY_P0_MPZQHWCTRL, enable both one-time &amp;amp; periodic HW ZQ calibration.&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;// For target board, may need to run write leveling calibration to fine tune these settings.&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b080c&amp;nbsp; 0x000E0000 &lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//Read DQS Gating calibration&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b083c 0x01480150 // MPDGCTRL0 PHY0&lt;BR /&gt;DATA 4 0x021b0840 0x00000000 // MPDGCTRL1 PHY0&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//Read calibration&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0848 0x40404E50 // MPRDDLCTL PHY0&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//Write calibration&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0850 0x40405048 // MPWRDLCTL PHY0&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b081c 0x33333333 // MMDC_MPRDDQBY0DL&lt;BR /&gt;DATA 4 0x021b0820 0x33333333 // MMDC_MPRDDQBY1DL&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//write data bit delay:&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b082c 0xF3333333 // MMDC_MPWRDQBY0DL&lt;BR /&gt;DATA 4 0x021b0830 0xF3333333 // MMDC_MPWRDQBY1DL&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//DQS&amp;amp;CLK Duty Cycle&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b08c0 0x00921012 // [MMDC_MPDCCR] MMDC Duty Cycle Control Register&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;// Complete calibration by forced measurement:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr&lt;BR /&gt;//=============================================================================&amp;nbsp; &amp;nbsp;&lt;BR /&gt;// Calibration setup end&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//=============================================================================&amp;nbsp; &amp;nbsp;&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//MMDC init:&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0004 0x0002002D // MMDC0_MDPDC&lt;BR /&gt;DATA 4 0x021b0008 0x1B333030 // MMDC0_MDOTC&lt;BR /&gt;DATA 4 0x021b000c 0x8B8F5333 // MMDC0_MDCFG0&lt;BR /&gt;DATA 4 0x021b0010 0xB68E0B63 // MMDC0_MDCFG1&lt;BR /&gt;DATA 4 0x021b0014 0x01FF00DB // MMDC0_MDCFG2&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//MDMISC: RALAT kept to the high level of 5.&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//a. better operation at low frequency, for LPDDR2 freq &amp;lt; 100MHz, change RALAT to 3&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//b. Small performence improvment&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0018 0x00211740 // MMDC0_MDMISC&lt;BR /&gt;DATA 4 0x021b001c 0x00008000 // MMDC0_MDSCR, set the Configuration request bit during MMDC set up&lt;BR /&gt;DATA 4 0x021b002c 0x000026D2 // MMDC0_MDRWD&lt;BR /&gt;DATA 4 0x021b0030 0x008F1023 // MMDC0_MDOR&lt;BR /&gt;DATA 4 0x021b0040 0x0000005F // Chan0 CS0_END &lt;BR /&gt;DATA 4 0x021b0000 0x85180000 // MMDC0_MDCTL&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0890 0x00400a38 // MPPDCMPR2&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//Mode register writes&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b001c 0x02008032 // MMDC0_MDSCR, MR2 write, CS0&lt;BR /&gt;DATA 4 0x021b001c 0x00008033 // MMDC0_MDSCR, MR3 write, CS0&lt;BR /&gt;DATA 4 0x021b001c 0x00048031 // MMDC0_MDSCR, MR1 write, CS0&lt;BR /&gt;DATA 4 0x021b001c 0x15208030 // MMDC0_MDSCR, MR0write, CS0&lt;BR /&gt;DATA 4 0x021b001c 0x04008040 // MMDC0_MDSCR, ZQ calibration command sent to device on CS0&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0020 0x00007800 // MMDC0_MDREF&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0818 0x00000227 // DDR_PHY_P0_MPODTCTRL&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0004 0x0002556D // MMDC0_MDPDC now SDCTL power down enabled&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0404 0x00011006 // MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 28 Nov 2019 00:28:49 GMT</pubDate>
    <dc:creator>nicholash</dc:creator>
    <dc:date>2019-11-28T00:28:49Z</dc:date>
    <item>
      <title>IMX6UL Linux/OPTEE Increasing RAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Linux-OPTEE-Increasing-RAM/m-p/982067#M145935</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm trying to get my board to recognise all my RAM, I had it recognising 128MB but I have 1GB installed. I have used the DDR configuration tool to configure uboot to configure the memory registers and it recognises the full amount of RAM. I can load an image onto the board using UUU, but on a restart I get the message "Starting kernel ..." from uBoot, then a few messages from OP-TEE starting, then the whole system hangs. From booting without my mods, I'd expect to get "Booting Linux on physical CPU 0x0". I have also CFG_DDR_SIZE in OP-TEE to 0x40000000.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What else do I need to configure?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Here is my memory configuration in uboot:&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;//=============================================================================&amp;nbsp; &amp;nbsp;&lt;BR /&gt;// Calibration setup.&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//=============================================================================&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0800 0xA1390003 // DDR_PHY_P0_MPZQHWCTRL, enable both one-time &amp;amp; periodic HW ZQ calibration.&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;// For target board, may need to run write leveling calibration to fine tune these settings.&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b080c&amp;nbsp; 0x000E0000 &lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//Read DQS Gating calibration&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b083c 0x01480150 // MPDGCTRL0 PHY0&lt;BR /&gt;DATA 4 0x021b0840 0x00000000 // MPDGCTRL1 PHY0&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//Read calibration&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0848 0x40404E50 // MPRDDLCTL PHY0&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//Write calibration&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0850 0x40405048 // MPWRDLCTL PHY0&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b081c 0x33333333 // MMDC_MPRDDQBY0DL&lt;BR /&gt;DATA 4 0x021b0820 0x33333333 // MMDC_MPRDDQBY1DL&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//write data bit delay:&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b082c 0xF3333333 // MMDC_MPWRDQBY0DL&lt;BR /&gt;DATA 4 0x021b0830 0xF3333333 // MMDC_MPWRDQBY1DL&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//DQS&amp;amp;CLK Duty Cycle&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b08c0 0x00921012 // [MMDC_MPDCCR] MMDC Duty Cycle Control Register&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;// Complete calibration by forced measurement:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr&lt;BR /&gt;//=============================================================================&amp;nbsp; &amp;nbsp;&lt;BR /&gt;// Calibration setup end&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//=============================================================================&amp;nbsp; &amp;nbsp;&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//MMDC init:&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0004 0x0002002D // MMDC0_MDPDC&lt;BR /&gt;DATA 4 0x021b0008 0x1B333030 // MMDC0_MDOTC&lt;BR /&gt;DATA 4 0x021b000c 0x8B8F5333 // MMDC0_MDCFG0&lt;BR /&gt;DATA 4 0x021b0010 0xB68E0B63 // MMDC0_MDCFG1&lt;BR /&gt;DATA 4 0x021b0014 0x01FF00DB // MMDC0_MDCFG2&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//MDMISC: RALAT kept to the high level of 5.&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//a. better operation at low frequency, for LPDDR2 freq &amp;lt; 100MHz, change RALAT to 3&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//b. Small performence improvment&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0018 0x00211740 // MMDC0_MDMISC&lt;BR /&gt;DATA 4 0x021b001c 0x00008000 // MMDC0_MDSCR, set the Configuration request bit during MMDC set up&lt;BR /&gt;DATA 4 0x021b002c 0x000026D2 // MMDC0_MDRWD&lt;BR /&gt;DATA 4 0x021b0030 0x008F1023 // MMDC0_MDOR&lt;BR /&gt;DATA 4 0x021b0040 0x0000005F // Chan0 CS0_END &lt;BR /&gt;DATA 4 0x021b0000 0x85180000 // MMDC0_MDCTL&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0890 0x00400a38 // MPPDCMPR2&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;//Mode register writes&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b001c 0x02008032 // MMDC0_MDSCR, MR2 write, CS0&lt;BR /&gt;DATA 4 0x021b001c 0x00008033 // MMDC0_MDSCR, MR3 write, CS0&lt;BR /&gt;DATA 4 0x021b001c 0x00048031 // MMDC0_MDSCR, MR1 write, CS0&lt;BR /&gt;DATA 4 0x021b001c 0x15208030 // MMDC0_MDSCR, MR0write, CS0&lt;BR /&gt;DATA 4 0x021b001c 0x04008040 // MMDC0_MDSCR, ZQ calibration command sent to device on CS0&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0020 0x00007800 // MMDC0_MDREF&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0818 0x00000227 // DDR_PHY_P0_MPODTCTRL&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0004 0x0002556D // MMDC0_MDPDC now SDCTL power down enabled&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b0404 0x00011006 // MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.&lt;BR /&gt;&amp;nbsp; &amp;nbsp;&lt;BR /&gt;DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 28 Nov 2019 00:28:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Linux-OPTEE-Increasing-RAM/m-p/982067#M145935</guid>
      <dc:creator>nicholash</dc:creator>
      <dc:date>2019-11-28T00:28:49Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6UL Linux/OPTEE Increasing RAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Linux-OPTEE-Increasing-RAM/m-p/982068#M145936</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Nick&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;one can try to boot without optee, in particular memory size can be adjusted&lt;/P&gt;&lt;P&gt;in uboot with #define PHYS_SDRAM_SIZE&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://source.codeaurora.org/external/imx/uboot-imx/tree/include/configs/mx6ul_14x14_evk.h?h=imx_v2018.03_4.14.98_2.2.0" title="https://source.codeaurora.org/external/imx/uboot-imx/tree/include/configs/mx6ul_14x14_evk.h?h=imx_v2018.03_4.14.98_2.2.0"&gt;mx6ul_14x14_evk.h\configs\include - uboot-imx - i.MX U-Boot&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 28 Nov 2019 09:07:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Linux-OPTEE-Increasing-RAM/m-p/982068#M145936</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-11-28T09:07:49Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6UL Linux/OPTEE Increasing RAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Linux-OPTEE-Increasing-RAM/m-p/982069#M145937</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor, &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have set PHYS_SDRAM_SIZE to&amp;nbsp;SZ_1G with no luck, I have the exact same problem.&lt;/P&gt;&lt;P&gt;I believe it does boot with if I disable OP-TEE, I need to use OP-TEE for my application though.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 28 Nov 2019 22:39:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Linux-OPTEE-Increasing-RAM/m-p/982069#M145937</guid>
      <dc:creator>nicholash</dc:creator>
      <dc:date>2019-11-28T22:39:53Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6UL Linux/OPTEE Increasing RAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Linux-OPTEE-Increasing-RAM/m-p/982070#M145938</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Nick&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/95332iAA0E9D32DC442976/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.jpg" alt="pastedImage_1.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;also one can look at similar issue on&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://github.com/OP-TEE/optee_os/issues/2313" title="https://github.com/OP-TEE/optee_os/issues/2313"&gt;Hikey 620: increase TA RAM in OP-TEE · Issue #2313 · OP-TEE/optee_os · GitHub&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 29 Nov 2019 00:44:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Linux-OPTEE-Increasing-RAM/m-p/982070#M145938</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-11-29T00:44:40Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6UL Linux/OPTEE Increasing RAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Linux-OPTEE-Increasing-RAM/m-p/982071#M145939</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor, &lt;BR /&gt;&lt;BR /&gt;I have solved this issue by pulling the latest version of imx-optee-os.&lt;/P&gt;&lt;P&gt;Evidently, this was solved in the last few months.&lt;/P&gt;&lt;P&gt;Thanks for your help.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 29 Nov 2019 04:59:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6UL-Linux-OPTEE-Increasing-RAM/m-p/982071#M145939</guid>
      <dc:creator>nicholash</dc:creator>
      <dc:date>2019-11-29T04:59:48Z</dc:date>
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