<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックiMX8QM SCU/M4 RGPIO Interrupt</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX8QM-SCU-M4-RGPIO-Interrupt/m-p/975950#M145236</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The iMX8QM has two M4 with their down peripherals. One of which is RGPIO or Rapid GPIO ( perhaps even Fast GPIO, FGPIO).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does the M4 GPIO block has interrupt support ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;It would appear not to be the case since the SDK for&amp;nbsp;the M4 cores do not have interrupt register.&amp;nbsp;&lt;/DIV&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;&lt;SPAN style="color: inherit; border: 0px;"&gt;/** GPIO - Register Layout Typedef */&lt;BR /&gt;&lt;/SPAN&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;typedef struct {&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __IO uint32_t PDOR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Data Output Register, offset: 0x0 */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __O &amp;nbsp;uint32_t PSOR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Set Output Register, offset: 0x4 */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __O &amp;nbsp;uint32_t PCOR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Clear Output Register, offset: 0x8 */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __O &amp;nbsp;uint32_t PTOR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Toggle Output Register, offset: 0xC */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __I &amp;nbsp;uint32_t PDIR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Data Input Register, offset: 0x10 */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __IO uint32_t PDDR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Data Direction Register, offset: 0x14 */&lt;/DIV&gt;&lt;SPAN style="color: inherit; border: 0px;"&gt;} GPIO_Type;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;&lt;SPAN style="border: 0px; color: inherit; "&gt;/** RGPIO - Register Layout Typedef */&lt;BR /&gt;&lt;/SPAN&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;typedef struct {&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __IO uint32_t PDOR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Data Output Register, offset: 0x0 */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __O &amp;nbsp;uint32_t PSOR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Set Output Register, offset: 0x4 */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __O &amp;nbsp;uint32_t PCOR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Clear Output Register, offset: 0x8 */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __O &amp;nbsp;uint32_t PTOR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Toggle Output Register, offset: 0xC */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __I &amp;nbsp;uint32_t PDIR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Data Input Register, offset: 0x10 */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __IO uint32_t PDDR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Data Direction Register, offset: 0x14 */&lt;/DIV&gt;&lt;SPAN style="border: 0px; color: inherit; "&gt;} RGPIO_Type;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;&lt;SPAN style="color: inherit; border: 0px;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;&lt;SPAN style="color: inherit; border: 0px;"&gt;Furthermore, the SDK for the M4 cores does not list any RGPIO interrupt vector :&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;&lt;SPAN style="border: 0px; color: inherit; "&gt; M4_0_TPM_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;= 19, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Timer PWM Module */&lt;BR /&gt;&lt;/SPAN&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; Reserved36_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;= 20, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Reserved */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; Reserved37_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;= 21, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Reserved */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; M4_0_LPIT_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; = 22, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Low-Power Periodic Interrupt Timer */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; Reserved39_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;= 23, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Reserved */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; Reserved40_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;= 24, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Reserved */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; M4_0_LPUART_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; = 25, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Low Power UART */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; Reserved42_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;= 26, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Reserved */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; M4_0_LPI2C_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;= 27, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Low-Power I2C - Logical OR of master and slave interrupts */&lt;/DIV&gt;&lt;SPAN style="border: 0px; color: inherit; "&gt;&amp;nbsp; Reserved44_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;= 28, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Reserved */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;&lt;/DIV&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;Is this correct ?&lt;/DIV&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;Is there any way to have GPIO interrupt in M4 firmware ? What are the constraints ?&lt;/DIV&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;&lt;/DIV&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;Regards,&lt;BR /&gt;Stan&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 03 Feb 2020 16:21:46 GMT</pubDate>
    <dc:creator>sbertrand</dc:creator>
    <dc:date>2020-02-03T16:21:46Z</dc:date>
    <item>
      <title>iMX8QM SCU/M4 RGPIO Interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8QM-SCU-M4-RGPIO-Interrupt/m-p/975950#M145236</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The iMX8QM has two M4 with their down peripherals. One of which is RGPIO or Rapid GPIO ( perhaps even Fast GPIO, FGPIO).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does the M4 GPIO block has interrupt support ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;It would appear not to be the case since the SDK for&amp;nbsp;the M4 cores do not have interrupt register.&amp;nbsp;&lt;/DIV&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;&lt;SPAN style="color: inherit; border: 0px;"&gt;/** GPIO - Register Layout Typedef */&lt;BR /&gt;&lt;/SPAN&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;typedef struct {&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __IO uint32_t PDOR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Data Output Register, offset: 0x0 */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __O &amp;nbsp;uint32_t PSOR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Set Output Register, offset: 0x4 */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __O &amp;nbsp;uint32_t PCOR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Clear Output Register, offset: 0x8 */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __O &amp;nbsp;uint32_t PTOR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Toggle Output Register, offset: 0xC */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __I &amp;nbsp;uint32_t PDIR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Data Input Register, offset: 0x10 */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __IO uint32_t PDDR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Data Direction Register, offset: 0x14 */&lt;/DIV&gt;&lt;SPAN style="color: inherit; border: 0px;"&gt;} GPIO_Type;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;&lt;SPAN style="border: 0px; color: inherit; "&gt;/** RGPIO - Register Layout Typedef */&lt;BR /&gt;&lt;/SPAN&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;typedef struct {&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __IO uint32_t PDOR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Data Output Register, offset: 0x0 */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __O &amp;nbsp;uint32_t PSOR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Set Output Register, offset: 0x4 */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __O &amp;nbsp;uint32_t PCOR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Clear Output Register, offset: 0x8 */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __O &amp;nbsp;uint32_t PTOR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Toggle Output Register, offset: 0xC */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __I &amp;nbsp;uint32_t PDIR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Data Input Register, offset: 0x10 */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; __IO uint32_t PDDR; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;/**&amp;lt; Port Data Direction Register, offset: 0x14 */&lt;/DIV&gt;&lt;SPAN style="border: 0px; color: inherit; "&gt;} RGPIO_Type;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;&lt;SPAN style="color: inherit; border: 0px;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;&lt;SPAN style="color: inherit; border: 0px;"&gt;Furthermore, the SDK for the M4 cores does not list any RGPIO interrupt vector :&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;&lt;SPAN style="border: 0px; color: inherit; "&gt; M4_0_TPM_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;= 19, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Timer PWM Module */&lt;BR /&gt;&lt;/SPAN&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; Reserved36_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;= 20, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Reserved */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; Reserved37_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;= 21, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Reserved */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; M4_0_LPIT_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; = 22, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Low-Power Periodic Interrupt Timer */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; Reserved39_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;= 23, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Reserved */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; Reserved40_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;= 24, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Reserved */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; M4_0_LPUART_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; = 25, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Low Power UART */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; Reserved42_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;= 26, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Reserved */&lt;/DIV&gt;&lt;DIV style="color: inherit; border: 0px;"&gt;&amp;nbsp; M4_0_LPI2C_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;= 27, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Low-Power I2C - Logical OR of master and slave interrupts */&lt;/DIV&gt;&lt;SPAN style="border: 0px; color: inherit; "&gt;&amp;nbsp; Reserved44_IRQn &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;= 28, &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /**&amp;lt; Reserved */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;&lt;/DIV&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;Is this correct ?&lt;/DIV&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;Is there any way to have GPIO interrupt in M4 firmware ? What are the constraints ?&lt;/DIV&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;&lt;/DIV&gt;&lt;DIV style="color: black; background-color: #ffffff; border: 0px; font-size: 12pt;"&gt;Regards,&lt;BR /&gt;Stan&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 03 Feb 2020 16:21:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8QM-SCU-M4-RGPIO-Interrupt/m-p/975950#M145236</guid>
      <dc:creator>sbertrand</dc:creator>
      <dc:date>2020-02-03T16:21:46Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8QM SCU/M4 RGPIO Interrupt</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8QM-SCU-M4-RGPIO-Interrupt/m-p/975951#M145237</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Stan&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: inherit; border: 0px;"&gt;RGPIO&lt;/SPAN&gt; module has not interrupt capability, opposed to GPIO module&lt;/P&gt;&lt;P&gt;in LSIO subsystem.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 04 Feb 2020 23:36:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8QM-SCU-M4-RGPIO-Interrupt/m-p/975951#M145237</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2020-02-04T23:36:48Z</dc:date>
    </item>
  </channel>
</rss>

