topic Re: imx6ull not booting after watchdog/core0 reset in i.MX Processors

imx6ull not booting after watchdog/core0 reset

kevincronn — Tue, 25 Jun 2019 18:01:21 GMT

I have a bare metal application with the single core imx6ull. We are trying to get the chip to reset and boot from qspi flash after a watchdog reset but the imx6 does not come back up after reset. If we power cycle it will boot ok. I have tried to reset with the watchdog and by enabling the core0 reset in the SRC_SCR.

Watchdog reset code:

// force cold reset.
SRC->SCR &= ~SRC_SCR_WARM_RESET_ENABLE_MASK;

// enable clock in CCM
if(base == (WDOG_Type *)WDOG1_BASE)
{
CCM->CCGR3 |= 0x30000;
}
else if(base == (WDOG_Type *)WDOG2_BASE)
{
CCM->CCGR5 |= 0xC00;
}
else if(base == (WDOG_Type *)WDOG3_BASE)
{
CCM->CCGR6 |= 0x300000;
}
else
{
return;
}

base->WICR = WDOG_WICR_WICT(0x00) | WDOG_WICR_WIE(0);
base->WMCR = WDOG_WMCR_PDE(0);
base->WCR = WDOG_WCR_WDE_MASK;

After writing the WDOG_WCR_WDE_MASK the system halts but never comes back.

Core0 code:

SRC->SCR |= 0xa0000;

Again after writing the core0 reset bit the system halts but never comes back.

Any help is appreciated.

Re: imx6ull not booting after watchdog/core0 reset

igorpadykov — Tue, 25 Jun 2019 23:58:01 GMT

Hi Kevin

recommended to remove power to the qspi as part of the processor reset, as it is done

in i.MX6ULL EVK schematic SPF-29364 signal nWDOG p.7, U708 p.10 :

MCIMX6ULL-EVK_DESIGNFILES

Design files, including hardware schematics, Gerbers, and OrCAD files.

Such solution places qspi to necessary state to support a reboot.

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

Re: imx6ull not booting after watchdog/core0 reset

kevincronn — Mon, 08 Jul 2019 18:17:17 GMT

Thank you Igor, we are evaluating changing our hardware design.