topic BT.656 line Interleave in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/BT-656-line-Interleave/m-p/968629#M144265 <HTML><HEAD></HEAD><BODY><P>We will connect 4 NTSC cameras to the video decoder IC like a below figure.</P><P>the video decoder IC merges multi-video streams into a single BT.656 output.</P><P></P><P><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/85875i9B75FA4C1E5EDF52/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /></span></P><P></P><P>In this case, Channel ID(CH ID) is embedded into EAV/SAV's least significant two bits such as below format.</P><P>Can i.MX8X series receive these data via parallel CSI interface?</P><P><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/85877i9A29E9ACA54682C9/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /></span></P><P></P><P>Best Regards,</P><P>Kazuma Sasaki.</P></BODY></HTML> Tue, 11 Jun 2019 05:27:21 GMT Kazuma_Sasaki 2019-06-11T05:27:21Z BT.656 line Interleave https://community.nxp.com/t5/i-MX-Processors/BT-656-line-Interleave/m-p/968629#M144265 <HTML><HEAD></HEAD><BODY><P>We will connect 4 NTSC cameras to the video decoder IC like a below figure.</P><P>the video decoder IC merges multi-video streams into a single BT.656 output.</P><P></P><P><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/85875i9B75FA4C1E5EDF52/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /></span></P><P></P><P>In this case, Channel ID(CH ID) is embedded into EAV/SAV's least significant two bits such as below format.</P><P>Can i.MX8X series receive these data via parallel CSI interface?</P><P><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/85877i9A29E9ACA54682C9/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /></span></P><P></P><P>Best Regards,</P><P>Kazuma Sasaki.</P></BODY></HTML> Tue, 11 Jun 2019 05:27:21 GMT https://community.nxp.com/t5/i-MX-Processors/BT-656-line-Interleave/m-p/968629#M144265 Kazuma_Sasaki 2019-06-11T05:27:21Z Re: BT.656 line Interleave https://community.nxp.com/t5/i-MX-Processors/BT-656-line-Interleave/m-p/968630#M144266 <HTML><HEAD></HEAD><BODY><P>i.mx8x support standard bt656 format, bt656 format EAV/SAV 8bits like: 1 F V H&nbsp; P3 P2 P1 P0</P><P></P><P><IMG alt="" border="0" src="http://img1.51cto.com/attachment/201104/200501427.jpg" style="border: 0px;" /></P></BODY></HTML> Tue, 18 Jun 2019 05:25:21 GMT https://community.nxp.com/t5/i-MX-Processors/BT-656-line-Interleave/m-p/968630#M144266 joanxie 2019-06-18T05:25:21Z Re: BT.656 line Interleave https://community.nxp.com/t5/i-MX-Processors/BT-656-line-Interleave/m-p/968631#M144267 <HTML><HEAD></HEAD><BODY><P>Hi Joan,</P><P></P><P>I appreciate your support. Okay, I got it. I will consider other solution.</P><P></P><P>Best Regards,<BR />Kazuma Sasaki.</P></BODY></HTML> Tue, 18 Jun 2019 08:28:13 GMT https://community.nxp.com/t5/i-MX-Processors/BT-656-line-Interleave/m-p/968631#M144267 Kazuma_Sasaki 2019-06-18T08:28:13Z