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    <title>topic Re: 1588 clock synchronization using ptp4l, but invalid in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965824#M143901</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello there;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;First of all, I am very grateful for your help to me during this time! But I still have problems.&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;1. I used two identical boards, one as the master clock and one as the slave clock. Using ptp4l for clock synchronization, the master offset value is around a single digit, but the system time has not changed.&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;2. "ptp hardware clock: 0" What is the meaning of this sentence? If it is 0, can you still perform hard timestamp synchronization? If not, then how can I solve this problem?&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Looking forward to your reply, thank you!&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/88680i56466357BBFEA1AF/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_3.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/88707i15486642D322716F/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_3.png" alt="pastedImage_3.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 03 Sep 2019 00:54:10 GMT</pubDate>
    <dc:creator>pengjing918</dc:creator>
    <dc:date>2019-09-03T00:54:10Z</dc:date>
    <item>
      <title>1588 clock synchronization using ptp4l, but invalid</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965815#M143892</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I use the officially provided image directly, support ethtool, ptp4l commands in the image, and support hard timestamps. ethtool executes as shown below:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_3.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/89133i4E8B980518B17ED9/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_3.png" alt="pastedImage_3.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;However, I use the ptp4l tool to perform clock synchronization. The master offset has been increasing and has been in the s0 state, as shown in the figure:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/89043iE5ACE4DA49E5453A/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Looking forward to your reply, thank you&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 23 Aug 2019 10:26:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965815#M143892</guid>
      <dc:creator>pengjing918</dc:creator>
      <dc:date>2019-08-23T10:26:53Z</dc:date>
    </item>
    <item>
      <title>Re: 1588 clock synchronization using ptp4l, but invalid</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965816#M143893</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The linux boot log is as follows:&lt;/P&gt;&lt;P&gt;pps_core: LinuxPPS API ver. 1 registered&lt;BR /&gt;pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti &amp;lt;giometti@linux.it&amp;gt;&lt;BR /&gt;PTP clock support registered&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Aug 2019 00:50:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965816#M143893</guid>
      <dc:creator>pengjing918</dc:creator>
      <dc:date>2019-08-27T00:50:55Z</dc:date>
    </item>
    <item>
      <title>Re: 1588 clock synchronization using ptp4l, but invalid</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965817#M143894</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The Linuxptp PTP stack implementation is supported in the current Linux BSP. For details, please refer to the Section 4.2 "ENET IEEE-1588" of the attached document.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;BR /&gt;Artur&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Aug 2019 10:27:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965817#M143894</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2019-08-27T10:27:15Z</dc:date>
    </item>
    <item>
      <title>Re: 1588 clock synchronization using ptp4l, but invalid</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965818#M143895</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/81571i200AEC2402FB7DAB/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;The manual says "By default, ENET 1588 is enabled.", however, the ptp4l command does not synchronize the clock.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 28 Aug 2019 00:49:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965818#M143895</guid>
      <dc:creator>pengjing918</dc:creator>
      <dc:date>2019-08-28T00:49:40Z</dc:date>
    </item>
    <item>
      <title>Re: 1588 clock synchronization using ptp4l, but invalid</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965819#M143896</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;What hardware (on both sides of the communication) and what exactly software do you use? Please specify.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 28 Aug 2019 05:27:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965819#M143896</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2019-08-28T05:27:04Z</dc:date>
    </item>
    <item>
      <title>Re: 1588 clock synchronization using ptp4l, but invalid</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965820#M143897</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Both ends of the communication use the imx6q chip, the mac layer 1588 communication, the software uses linuxptp&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Aug 2019 01:03:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965820#M143897</guid>
      <dc:creator>pengjing918</dc:creator>
      <dc:date>2019-08-29T01:03:42Z</dc:date>
    </item>
    <item>
      <title>Re: 1588 clock synchronization using ptp4l, but invalid</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965821#M143898</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Is Linux, running on your hardware, based on some Linux BSP by NXP? If so, which one is used (specify the kernel version and release number).&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Aug 2019 10:44:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965821#M143898</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2019-08-29T10:44:48Z</dc:date>
    </item>
    <item>
      <title>Re: 1588 clock synchronization using ptp4l, but invalid</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965822#M143899</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;STRONG&gt;ptp4l slave&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Linux imx6 3.14.52-rt52+g5f6f0a5 #2 SMP PREEMPT RT Fri Aug 2 12:21:15 CST 2019 armv7l GNU/Linux&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;ptp4l host&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Linux imx6qsabresd 4.1.15-00017-gf94be3a-dirty #1 SMP PREEMPT Mon Dec 3 16:20:20 CST 2018 armv7l armv7l armv7l GNU/Linux&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Like the two board chips, the core board is different.&lt;/P&gt;&lt;P&gt;As mentioned above, after the two boards start linux, the log shows that they all support ptp clock.&lt;/P&gt;&lt;P&gt;However, using the ptp4l command in the manual, hard clock synchronization is invalid.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 30 Aug 2019 01:07:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965822#M143899</guid>
      <dc:creator>pengjing918</dc:creator>
      <dc:date>2019-08-30T01:07:35Z</dc:date>
    </item>
    <item>
      <title>Re: 1588 clock synchronization using ptp4l, but invalid</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965823#M143900</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Actually, PTP is not properly implemented in the 3.14.52 BSP. Better is to migrate to latest 4.14.98 BSP on both Host and Slave boards.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 30 Aug 2019 06:58:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965823#M143900</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2019-08-30T06:58:35Z</dc:date>
    </item>
    <item>
      <title>Re: 1588 clock synchronization using ptp4l, but invalid</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965824#M143901</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello there;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;First of all, I am very grateful for your help to me during this time! But I still have problems.&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;1. I used two identical boards, one as the master clock and one as the slave clock. Using ptp4l for clock synchronization, the master offset value is around a single digit, but the system time has not changed.&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;2. "ptp hardware clock: 0" What is the meaning of this sentence? If it is 0, can you still perform hard timestamp synchronization? If not, then how can I solve this problem?&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Looking forward to your reply, thank you!&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/88680i56466357BBFEA1AF/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_3.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/88707i15486642D322716F/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_3.png" alt="pastedImage_3.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 03 Sep 2019 00:54:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965824#M143901</guid>
      <dc:creator>pengjing918</dc:creator>
      <dc:date>2019-09-03T00:54:10Z</dc:date>
    </item>
    <item>
      <title>Re: 1588 clock synchronization using ptp4l, but invalid</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965825#M143902</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;1. Since the master offset time units are nanoseconds, the clock adjustment may just be too small to be reflected in the standard system time representation.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2. "PTP Hardware Clock: 0" is just the mnemonic name of the hardware clock selected. You can perform the hard timestamp synchronization.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Some general PTP management information can be found, for example, here:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://doc.opensuse.org/documentation/leap/tuning/html/book.sle.tuning/cha.tuning.ptp.html" title="https://doc.opensuse.org/documentation/leap/tuning/html/book.sle.tuning/cha.tuning.ptp.html"&gt;Precision Time Protocol | System Analysis and Tuning Guide | openSUSE Leap 15.1&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 03 Sep 2019 08:24:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965825#M143902</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2019-09-03T08:24:36Z</dc:date>
    </item>
    <item>
      <title>Re: 1588 clock synchronization using ptp4l, but invalid</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965826#M143903</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Artur,&lt;BR /&gt;What I need to implement is the MAC layer of 1588.&lt;BR /&gt;1. "but the system time has not changed."; The slave has a time difference with the host, but after synchronization, there is still a time difference between the slave and the host, and the difference is unchanged.&lt;BR /&gt;2. I saw a lot of discussions about 1588 clock synchronization in the forum. There are some points that I don't understand.&lt;BR /&gt;1&amp;gt; I need to define MX6QDL_PAD_GPIO_16__ENET_REF_CLK, what does it mean?&lt;BR /&gt;2&amp;gt; What does 1PPS mean? Is there a frame of synchronized data every second?&lt;BR /&gt;3&amp;gt; Do I need to configure GPIO_19 as ENET_1588_EVENT0_OUT?&lt;BR /&gt;4&amp;gt; In the IMX6DQRM.pdf manual, 23.3 External Signals section says ENET_1588_EVENT0_IN and ENET_1588_EVENT0_OUT, do I need to configure it? If so, how do I configure it?&lt;BR /&gt;There are a lot of questions, please reply in detail, or be able to provide a detailed documentation on the configuration of MAC 1588. Thank you!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 04 Sep 2019 11:03:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965826#M143903</guid>
      <dc:creator>pengjing918</dc:creator>
      <dc:date>2019-09-04T11:03:20Z</dc:date>
    </item>
    <item>
      <title>Re: 1588 clock synchronization using ptp4l, but invalid</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965827#M143904</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Sep 2019 06:52:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965827#M143904</guid>
      <dc:creator>pengjing918</dc:creator>
      <dc:date>2019-09-10T06:52:17Z</dc:date>
    </item>
    <item>
      <title>Re: 1588 clock synchronization using ptp4l, but invalid</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965828#M143905</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The IEEE 1588 protocol is completely implemented in the Linux driver, there is nothing to add here.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The protocol only synchronizes the hardware clock frequencies, not the time counter values.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Sep 2019 11:10:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965828#M143905</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2019-09-12T11:10:54Z</dc:date>
    </item>
    <item>
      <title>Re: 1588 clock synchronization using ptp4l, but invalid</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965829#M143906</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Hi Artur,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Thank you for your reply&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;As you said, the 1588 protocol has been implemented. I used ptp4l + phc2sys to achieve time synchronization between the two hosts. Using the date command, the time is consistent. But I still have some questions.&lt;BR /&gt;1. Synchronize the clock frequency only, how is the time synchronized? Do you have trouble explaining the relationship between clock frequency and time stamp? Thank you&lt;BR /&gt;2. Can I get the PHC time directly? The following code:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;#define PTP_CLOCK_0_PATH "/dev/ptp0"&lt;/P&gt;&lt;P&gt;int main()&lt;BR /&gt;{&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;int ptp_clk_id = open(PTP_CLOCK_0_PATH, O_RDONLY);&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;if(ptp_clk_id == -1){&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;printf("ptp clock open fail\n");&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;return -1;&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;}&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;struct timespec ts;&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;clock_gettime(ptp_clk_id, &amp;amp;ts);//CLOCK_REALTIME&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;printf("ptp clock open ok\n");&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;printf("ts.tv_sec: %ld, ts.tv_nsec: %ld\n", ts.tv_sec, ts.tv_nsec);&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;close(ptp_clk_id);&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;return 0;&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;The results are as follows:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;root@imx6qsabresd:/mnt/test# ./ptp_clock_time &lt;BR /&gt;ptp clock open ok&lt;BR /&gt;ts.tv_sec: 0, ts.tv_nsec: 9609002&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 06 Oct 2019 08:43:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/1588-clock-synchronization-using-ptp4l-but-invalid/m-p/965829#M143906</guid>
      <dc:creator>pengjing918</dc:creator>
      <dc:date>2019-10-06T08:43:29Z</dc:date>
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