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    <title>i.MX ProcessorsのトピックRe: 8MMINILPD4-EVK Schematic question for note on pull up/down</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/8MMINILPD4-EVK-Schematic-question-for-note-on-pull-up-down/m-p/965554#M143859</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Jeff Freeman,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Details on the reason behind this note can be found on the i.MX8MM Erratum e50080 (link below, you may need to login to download this file).&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com/webapp/Download?colCode=IMX8MM_0N87W"&gt;https://www.nxp.com/webapp/Download?colCode=IMX8MM_0N87W&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The default configuration for most pins is the resistor pull enabled so you would need to disable these. You can see the default configuration for each pin on the &amp;nbsp;i.MX8MM Reference Manual (link below) on each of the pads registers. The variable is PE (Pull Resistors Enable Field)&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com/webapp/Download?colCode=IMX8MMRM"&gt;https://www.nxp.com/webapp/Download?colCode=IMX8MMRM&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope this helps!&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 26 Jul 2019 20:03:58 GMT</pubDate>
    <dc:creator>gusarambula</dc:creator>
    <dc:date>2019-07-26T20:03:58Z</dc:date>
    <item>
      <title>8MMINILPD4-EVK Schematic question for note on pull up/down</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/8MMINILPD4-EVK-Schematic-question-for-note-on-pull-up-down/m-p/965553#M143858</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;There is a note about "&lt;SPAN style="color: red; background: white; font-size: 10.0pt; "&gt;IO internal pull up/down is not supported in 3.3V mode, must disable the internal pull up/down&amp;nbsp;via software and use external pull up/down resistors instead.&lt;/SPAN&gt;". What is the default? And how are these to be disabled?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 25 Jul 2019 01:46:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/8MMINILPD4-EVK-Schematic-question-for-note-on-pull-up-down/m-p/965553#M143858</guid>
      <dc:creator>jefflfree</dc:creator>
      <dc:date>2019-07-25T01:46:26Z</dc:date>
    </item>
    <item>
      <title>Re: 8MMINILPD4-EVK Schematic question for note on pull up/down</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/8MMINILPD4-EVK-Schematic-question-for-note-on-pull-up-down/m-p/965554#M143859</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Jeff Freeman,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Details on the reason behind this note can be found on the i.MX8MM Erratum e50080 (link below, you may need to login to download this file).&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com/webapp/Download?colCode=IMX8MM_0N87W"&gt;https://www.nxp.com/webapp/Download?colCode=IMX8MM_0N87W&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The default configuration for most pins is the resistor pull enabled so you would need to disable these. You can see the default configuration for each pin on the &amp;nbsp;i.MX8MM Reference Manual (link below) on each of the pads registers. The variable is PE (Pull Resistors Enable Field)&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com/webapp/Download?colCode=IMX8MMRM"&gt;https://www.nxp.com/webapp/Download?colCode=IMX8MMRM&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope this helps!&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 26 Jul 2019 20:03:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/8MMINILPD4-EVK-Schematic-question-for-note-on-pull-up-down/m-p/965554#M143859</guid>
      <dc:creator>gusarambula</dc:creator>
      <dc:date>2019-07-26T20:03:58Z</dc:date>
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