<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックEthernet PHY</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Ethernet-PHY/m-p/959892#M143275</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hi&lt;/P&gt;&lt;P&gt;i am designed a custom i.mx6 based board with atheros PHY(ref is Sabre SD board)&lt;/P&gt;&lt;P&gt;Ehternet link is not established (auto negotiation is not working properly)&lt;/P&gt;&lt;P&gt;some times link is establishing and transmitting with missing packets&lt;/P&gt;&lt;P&gt;when i do restart it is not establishing the link&lt;/P&gt;&lt;P&gt;what could be the problem ?&lt;/P&gt;&lt;P&gt;is any pcb guide lines should i follow ?&lt;/P&gt;&lt;P&gt;thanks and regards&lt;/P&gt;&lt;P&gt;saida&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 07 Jun 2019 05:23:36 GMT</pubDate>
    <dc:creator>saida</dc:creator>
    <dc:date>2019-06-07T05:23:36Z</dc:date>
    <item>
      <title>Ethernet PHY</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Ethernet-PHY/m-p/959892#M143275</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hi&lt;/P&gt;&lt;P&gt;i am designed a custom i.mx6 based board with atheros PHY(ref is Sabre SD board)&lt;/P&gt;&lt;P&gt;Ehternet link is not established (auto negotiation is not working properly)&lt;/P&gt;&lt;P&gt;some times link is establishing and transmitting with missing packets&lt;/P&gt;&lt;P&gt;when i do restart it is not establishing the link&lt;/P&gt;&lt;P&gt;what could be the problem ?&lt;/P&gt;&lt;P&gt;is any pcb guide lines should i follow ?&lt;/P&gt;&lt;P&gt;thanks and regards&lt;/P&gt;&lt;P&gt;saida&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 07 Jun 2019 05:23:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Ethernet-PHY/m-p/959892#M143275</guid>
      <dc:creator>saida</dc:creator>
      <dc:date>2019-06-07T05:23:36Z</dc:date>
    </item>
    <item>
      <title>Re: Ethernet PHY</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Ethernet-PHY/m-p/959893#M143276</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Saida&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;one can check rgmii timings with oscilloscope using&lt;/P&gt;&lt;P&gt;Table 58. RGMII Signal Switching Specifications i.MX6Q Satasheet&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf" title="https://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf"&gt;https://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;and hardware requirements described in Hardware Guide&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/webapp/Download?colCode=IMX6DQ6SDLHDG" title="https://www.nxp.com/webapp/Download?colCode=IMX6DQ6SDLHDG"&gt;https://www.nxp.com/webapp/Download?colCode=IMX6DQ6SDLHDG&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 07 Jun 2019 10:21:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Ethernet-PHY/m-p/959893#M143276</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-06-07T10:21:35Z</dc:date>
    </item>
  </channel>
</rss>

