topic Re: i.MX8M DDR3L register programming aid difference in i.MX Processors

i.MX8M DDR3L register programming aid difference

m_c — Tue, 23 Jul 2019 10:33:50 GMT

There are two i.MX8M DDR3L register programming aid.

Old is MX8M_DDR3L_register_programming_aid_VAL_preliminiary_v1_2.xlsx from <https://community.nxp.com/docs/DOC-340268>.

New is MX8M_DDR3L_RPA_v6.xlsx from <https://community.nxp.com/docs/DOC-340179>.

May we know more detail about below two modifications?

1. New “K18”, it is related to “C175” & “D175” and the result will be changed for “0x3D400120”

2. Disable DDRC_DFIPHYMSTR in the latest version “6”, but in previous v1.2, the value is “1” that means the DDRC_DFIPHYMSTR is enabled. Should we set value to “0”?

Re: i.MX8M DDR3L register programming aid difference

gusarambula — Tue, 23 Jul 2019 19:26:49 GMT

Hello M.C.

I’m looking for more information on the changes between both versions. I will let you know as soon as I have an update.

Regards,

Re: i.MX8M DDR3L register programming aid difference

gusarambula — Wed, 24 Jul 2019 15:24:54 GMT

Hello M.C.

Some details on the changes between revisions can be found on the Revision History sheet.

As for your questions this is the information I received from our experts:

1. IP vendor ticket STAR 9001091272 dictates that we should set DRAMTMG8.t_xs_x32 = DRAMTMG8.t_xs_dll_x32 to avoid timing violations from SRX to PDE in DDR3.

2. Disabled DDRC_DFIPHYMSTR.DFI_PHYMSTR_EN as it is not used for DDR3L PHY firmware.

As a side note, it’s always recommended to use the latest version of the programming aid.

Regards,