i.MX ProcessorsのトピックIMX6ULL with codec MAX98090

IMX6ULL with codec MAX98090

dc1 — Wed, 23 Oct 2019 08:20:14 GMT

Hello all,

i need to configure the IMX pin that control the LRCLK pin of the MAX98090 as outpout beacuse i have problem with the clock signal levels. For the MCLK we have do that in this way:

how can i do the same for the LRCLK pin that is connected to the SAI_SYNC pin?

Thanks

Re: IMX6ULL with codec MAX98090

igorpadykov — Wed, 23 Oct 2019 10:14:27 GMT

Hi Daniele

one can look at i.MX6ULL EVK wm8960 example :

imx6ull-14x14-evk.dts\dts\boot\arm\arch - linux-imx - i.MX Linux kernel

i.MX6ULL EVK schematic

Design files, including hardware schematics, Gerbers, and OrCAD files

may be useful to check sai dts documentation:

fsl-sai.txt\sound\bindings\devicetree\Documentation - linux-imx - i.MX Linux kernel

Best regards
igor
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Re: IMX6ULL with codec MAX98090

dc1 — Thu, 24 Oct 2019 08:16:48 GMT

Hello,

thanks we are trying to understand if the configuration of the pins is correct for our MAX98090 that is different from the wm8960 . We have set the fsl,pins in this way:

pinctrl_sai2: sai2grp {
                        fsl,pins = <
                                MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x170A1
                                MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x170A1
                                MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x110A0
                                MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x110A0
                                MX6UL_PAD_JTAG_TMS__SAI2_MCLK           0x170A1
                        >;
                };

reducing the DSE resistence and enabling the fast slew rate

we have seen that the PAD define are:

/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/

#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01C0 0x044C 0x05F0 0x2 0x1

#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x01C4 0x0450 0x05FC 0x2 0x1

#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x01C8 0x0454 0x05F8 0x2 0x1

#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x01CC 0x0458 0x05F4 0x2 0x1

#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x01D0 0x045C 0x0000 0x2 0x0

with the value written in the fsl,pins (for example the 0x170A1) we are going to over-write a value of the #define here upper or what?

Thanks

Re: IMX6ULL with codec MAX98090

igorpadykov — Thu, 24 Oct 2019 10:06:16 GMT

so had you checked signals with oscilloscope,

do they suit MAX98090 datasheet requirements ?

Best regards
igor

Re: IMX6ULL with codec MAX98090

dc1 — Fri, 25 Oct 2019 09:48:50 GMT

Hello,

we are trying to increase the clock signal quality changing the DSE configuration of the pins following the guide on pag 19 of this document https://docs.toradex.com/104446-colibri-arm-som-imx6ull-datasheet.pdf

Thanks