ONOFFpin debounce time

goto11 — Tue, 08 Oct 2019 00:23:21 GMT

hello,Community

The i.MX 7 Dual Applications Processor Reference Manual Dumb PMIC mode is described as follows.

Debounce—the debounce configuration supports 0 ms, 50 ms, 100 ms, and 500 ms.
The debounce is used to generate the set_pwr_off_irq interrupt. While it is in the ON state and the button is pressed longer than the debounce time, the set_pwr_off_irq is generated.

On the other hand, Figure 6-7. About FSM
The condition for transition from the OFF state is described as button pressed (any duration).
Can the debounce time be set in the same register for the transition from the ON state and the transition from the OFF state?

best regards

Goto

Re: ONOFFpin debounce time

gusarambula — Tue, 08 Oct 2019 16:58:46 GMT

Hello Goto,

The debounce mechanism works for both transitions as you can see in Figure 6-6. Once after the Power-On Reset the debounced is used to avoid false readings to turn ON and OFF, and it’s the one configured for the “power off” interrupt. It cannot be set independently for each transition.

I hope this helps!
Regards,

topic Re: ONOFFpin debounce time in i.MX Processors

ONOFFpin debounce time

Re: ONOFFpin debounce time