i.MX ProcessorsのトピックRe: 32bit bus width memory with 2 cs in IMX6Q

32bit bus width memory with 2 cs in IMX6Q

stevetsai — Sun, 30 Dec 2012 13:39:13 GMT

I am porting software with a board using IMX6Q which built in 2GB DDR3 memory. The board uses 32 bits memory bus instead of 64 bits memory bus, and it uses two CS signals to select these chips. I can setup 32 bits mode with 1GB memory, but I got the problem when I try to use CS1. It means that I can run Linux with 1G memory, but I can not run the kernel with 2G memory. The following are the settings I am using. Does anyone use the same DDR configuration successfully?

MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)

MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0xC4190000)

MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)

MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x0408803A)

MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)

MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B)

MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)

MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)

MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)

MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x01c, 0x09408038)

MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)

MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)

Re: 32bit bus width memory with 2 cs in IMX6Q

stevetsai — Thu, 03 Jan 2013 01:59:48 GMT

From the following article from freescale, CS0 and CS1 use the same calibration registers, so they should have the same traces. What are the skew of the two group?

The user has the option of populating DDR memory devices on chip select 0 (CSD0), chip select 1 (CSD1), or both chip selects. The control mechanism to decide which chip select the associated calibration is targeted to is found in MDMISC[CALIB_PER_CS] bit. If the DDR memory devices are populated on CSD0, then this bit would be cleared. If these devices are populated only on CSD1, then this bit would be set. Should both chip selects be populated, it is an absolute must that the memories populated on CSD1 are “mirrored” with the memories populated on CSD0, as both CSD share the same delay line register set during normal DDR operation. Given the similarities in memory device layout, either setting can be used for MDMISC[CALIB_PER_CS] bit. However, the examples in this document clear this bit, hence targeting calibration toward CSD0

Re: 32bit bus width memory with 2 cs in IMX6Q

stevetsai — Tue, 05 Feb 2013 17:15:32 GMT

You have to calibrate the memory according to CS0 or CS1 and use these configurations from your calibration. The 2GB DDR3 is working now.

Re: 32bit bus width memory with 2 cs in IMX6Q

kevin_chan — Thu, 09 May 2013 01:53:07 GMT

hi, stevetsai

i have the same problem now, can you help me , thanks!

we have designed imx6 board with this ddr setting:

512MB per chip select, total 1GB, 32bit data bus.

when use DDR_STRESS_TEST tools to test:

if just select cs0, 512MB size per chip select, then can pass the test.

but if select both cs0 & cs1, 512MB size per chip select, it failed.

anyway, i can't enable 1GB ddr3 with two chip select now!

Re: 32bit bus width memory with 2 cs in IMX6Q

stevetsai — Tue, 14 May 2013 11:45:56 GMT

Please refer to the i,MX6 reference manual to calibrate the DQS gating, read adn write delay for CS1. Then find out these values for CS0 and CS1.

Re: 32bit bus width memory with 2 cs in IMX6Q

kevin_chan — Wed, 15 May 2013 07:42:14 GMT

thanks for your suggestion , i would check iMX6 reference manual about CS1's calibrate. then try your method.

which version is your i.MX6 reference manual? i have "Rev. 1, 04/2013" now.

before see your discussion,i nearly give up this design,

because in i.MX6 reference manual there are these words:

"The core is composed of two channels, but both channels are only active in LPDDR2 mode. If DDR3 mode is selected,channel1 is not activated and the MMDC communicates with the system through AXI port0."

---- quote from Chapter 44 : Multi Mode DDR Controller (MMDC)

thank you very much.

Re: 32bit bus width memory with 2 cs in IMX6Q

stevetsai — Thu, 16 May 2013 00:51:22 GMT

You can use CS1, but MMDC communicate with CS0 and CS1 via P0 only. It means that you only can calibrate ether CS0 or CS1 only with P0 and use these values accepted by CS0 and CS1. If the value you get from CS0 is 10 and the value you get is 20 from CS1, then you have try these values from 10 to 20. You have to design and layout both CS0 group and CS1 group in the same way, if you want to use CS0 and CS1.

Re: 32bit bus width memory with 2 cs in IMX6Q

kevin_chan — Fri, 17 May 2013 03:08:52 GMT

i have try by this:

set MDMISC[CALIB_PER_CS] to 0, use ddr_stress_test tool to calibrate and test cs0 with 512MB per chip select. it can pass.

then set MDMISC[CALIB_PER_CS] to 1, to calibrate and test cs1 with 512MB per chip select. it fail:

*******************************************************************************

Error flags: read_dqs_gating: 1, read cal: 1, write cal: 1

**re-running calibration did not resolve, check hw or code

DDR Freq: 528 MHz

MMDC registers updated from calibration

Read DQS Gating calibration

MPDGCTRL0 PHY0 (0x021b083c) = 0x4E001E00

MPDGCTRL1 PHY0 (0x021b0840) = 0x0E000E00

Read calibration

MPRDDLCTL PHY0 (0x021b0848) = 0x40404040

Write calibration

MPWRDLCTL PHY0 (0x021b0850) = 0x40404040

** Error detected during calibration

Error flags: read_dqs_gating: 1, read cal: 1, write cal: 1

>> Attempting to run calibration one more time

MMDC registers updated from calibration

Read DQS Gating calibration

MPDGCTRL0 PHY0 (0x021b083c) = 0x4E001E00

MPDGCTRL1 PHY0 (0x021b0840) = 0x0E000E00

Read calibration

MPRDDLCTL PHY0 (0x021b0848) = 0x40404040

Write calibration

MPWRDLCTL PHY0 (0x021b0850) = 0x40404040

** Error detected during calibration

Error flags: read_dqs_gating: 1, read cal: 1, write cal: 1

**re-running calibration did not resolve, check hw or code

*******************************************************************************

is my way right? i just change MDMISC[CALIB_PER_CS] to 1. i am confused.

Re: 32bit bus width memory with 2 cs in IMX6Q

stevetsai — Fri, 17 May 2013 09:03:37 GMT

I did not use ddr_stress_tool, so I did not know how to set these parameters. But the program has to set MDMISC, MDSCR and MDCTL to use CS1 instead of CS0. By the way, make sure that you just calibrate 32 bits bus.

Re: 32bit bus width memory with 2 cs in IMX6Q

massimo2 — Tue, 15 Oct 2019 10:06:12 GMT

Hello
I'm looking for hints.
I'm trying to put 4 DDR3 chips in my design. Do you think there will be an advantage using CS0/CS1 chip select (2x32bit data bus) instead only one chip select for all DDR3 memories(all 64 data bits on same CS)?

Thank you in advance.