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    <title>i.MX ProcessorsのトピックAbout MCIMX8M-EVKB design</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/About-MCIMX8M-EVKB-design/m-p/951878#M142281</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;1) As Per schematics file on page no 12, there are Four capacitors C929, C930, C931 and C932 (High lighted in below image) added on VSYS 12V power rail: My question here is the total some of capacitance is 100uf only but why these four caps added in schematics? what is the purpose?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/83199iB55BE14551A4A056/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2)&amp;nbsp; As per same schematics why the USB J903 connector VBUS current is limited to 2.1A, any specific use case? (Refer below image)&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/83458iA36DDFEE2BCE71A2/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;3) In WiFi/BT section, U1301B as per LBEH5IL1CX datasheet: &lt;SPAN style="left: 96.8472px; top: 134.837px; font-size: 17.0111px; font-family: sans-serif; transform: scaleX(0.984426);"&gt;VBAT should be up b&lt;/SPAN&gt;&lt;SPAN style="left: 253.845px; top: 134.837px; font-size: 17.0111px; font-family: sans-serif; transform: scaleX(0.982473);"&gt;efore or at the same time as VIO. VIO&lt;/SPAN&gt; &lt;SPAN style="left: 537.895px; top: 134.837px; font-size: 17.0111px; font-family: sans-serif; transform: scaleX(0.987643);"&gt;should NOT be present first&lt;/SPAN&gt; &lt;SPAN style="left: 747.682px; top: 134.837px; font-size: 17.0111px; font-family: sans-serif; transform: scaleX(0.985445);"&gt;or be held high&lt;/SPAN&gt; &lt;SPAN style="left: 91.2413px; top: 154.361px; font-size: 17.0111px; font-family: sans-serif; transform: scaleX(0.992762);"&gt;before VBAT is high&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="left: 91.2413px; top: 154.361px; font-size: 17.0111px; font-family: sans-serif; transform: scaleX(0.992762);"&gt;In Schematics power sequence: VDD_3V3 (VIO) rails is power up first than DCDC_5V(VBAT) rail will going to up (U706, DCDC 5V module is Enable from VDD_3V3 rail), this will leads to wrong power up sequence can you just clarify on this?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/83547i95904386DDA6AC33/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_3.png" alt="pastedImage_3.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 05 Sep 2019 07:58:06 GMT</pubDate>
    <dc:creator>nadira</dc:creator>
    <dc:date>2019-09-05T07:58:06Z</dc:date>
    <item>
      <title>About MCIMX8M-EVKB design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-MCIMX8M-EVKB-design/m-p/951878#M142281</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;1) As Per schematics file on page no 12, there are Four capacitors C929, C930, C931 and C932 (High lighted in below image) added on VSYS 12V power rail: My question here is the total some of capacitance is 100uf only but why these four caps added in schematics? what is the purpose?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/83199iB55BE14551A4A056/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2)&amp;nbsp; As per same schematics why the USB J903 connector VBUS current is limited to 2.1A, any specific use case? (Refer below image)&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/83458iA36DDFEE2BCE71A2/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;3) In WiFi/BT section, U1301B as per LBEH5IL1CX datasheet: &lt;SPAN style="left: 96.8472px; top: 134.837px; font-size: 17.0111px; font-family: sans-serif; transform: scaleX(0.984426);"&gt;VBAT should be up b&lt;/SPAN&gt;&lt;SPAN style="left: 253.845px; top: 134.837px; font-size: 17.0111px; font-family: sans-serif; transform: scaleX(0.982473);"&gt;efore or at the same time as VIO. VIO&lt;/SPAN&gt; &lt;SPAN style="left: 537.895px; top: 134.837px; font-size: 17.0111px; font-family: sans-serif; transform: scaleX(0.987643);"&gt;should NOT be present first&lt;/SPAN&gt; &lt;SPAN style="left: 747.682px; top: 134.837px; font-size: 17.0111px; font-family: sans-serif; transform: scaleX(0.985445);"&gt;or be held high&lt;/SPAN&gt; &lt;SPAN style="left: 91.2413px; top: 154.361px; font-size: 17.0111px; font-family: sans-serif; transform: scaleX(0.992762);"&gt;before VBAT is high&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="left: 91.2413px; top: 154.361px; font-size: 17.0111px; font-family: sans-serif; transform: scaleX(0.992762);"&gt;In Schematics power sequence: VDD_3V3 (VIO) rails is power up first than DCDC_5V(VBAT) rail will going to up (U706, DCDC 5V module is Enable from VDD_3V3 rail), this will leads to wrong power up sequence can you just clarify on this?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/83547i95904386DDA6AC33/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_3.png" alt="pastedImage_3.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 05 Sep 2019 07:58:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-MCIMX8M-EVKB-design/m-p/951878#M142281</guid>
      <dc:creator>nadira</dc:creator>
      <dc:date>2019-09-05T07:58:06Z</dc:date>
    </item>
    <item>
      <title>Re: About MCIMX8M-EVKB design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-MCIMX8M-EVKB-design/m-p/951879#M142282</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A _jive_internal="true" data-content-finding="Community" data-userid="313796" data-username="nadira" href="https://community.nxp.com/people/nadira"&gt;Yaseen&lt;/A&gt;,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; See below, please!&lt;/P&gt;&lt;P&gt;1. When two capacitors of the same capacity are connected in series, their rating voltage will double, but the capacitance will be reduced by half. So the purpose of this connection is to improve rating voltage.&lt;/P&gt;&lt;P&gt;2. The rating current of USB connectors should not exceed 2.1A&lt;/P&gt;&lt;P&gt;3. According to the LBEH5IL1CX data sheet, what you said is correct. However, after EVK verification, EVK's LBEH5IL1CX power-on sequence is not a problem, so there is no need to worry about this problem.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hope above information is helpful for you!&lt;/P&gt;&lt;P&gt;Have a nice day!&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Weidong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Sep 2019 03:32:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-MCIMX8M-EVKB-design/m-p/951879#M142282</guid>
      <dc:creator>weidong_sun</dc:creator>
      <dc:date>2019-09-12T03:32:08Z</dc:date>
    </item>
    <item>
      <title>Re: About MCIMX8M-EVKB design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-MCIMX8M-EVKB-design/m-p/951880#M142283</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Weidong,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1 and 2 query i understood Thanks for reply,&lt;/P&gt;&lt;P&gt;However for 2nd Query: USB 3.0 Host Max port current is 900mA only, here my question is any specific reason to set here current limit for 2.1A, any USB 3.0 Host device consume up to 2.1A current?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yaseen&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Sep 2019 07:15:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-MCIMX8M-EVKB-design/m-p/951880#M142283</guid>
      <dc:creator>nadira</dc:creator>
      <dc:date>2019-09-16T07:15:55Z</dc:date>
    </item>
    <item>
      <title>Re: About MCIMX8M-EVKB design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-MCIMX8M-EVKB-design/m-p/951881#M142284</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A _jive_internal="true" class="" data-containerid="-1" data-containertype="-1" data-content-finding="Community" data-objectid="313796" data-objecttype="3" href="https://community.nxp.com/people/nadira"&gt;Yaseen&lt;/A&gt;,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; The current is determined by the USB connector you select.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a nice day!&lt;/P&gt;&lt;P&gt;BR,&lt;/P&gt;&lt;P&gt;Weidong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Sep 2019 09:26:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-MCIMX8M-EVKB-design/m-p/951881#M142284</guid>
      <dc:creator>weidong_sun</dc:creator>
      <dc:date>2019-09-16T09:26:43Z</dc:date>
    </item>
    <item>
      <title>Re: About MCIMX8M-EVKB design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-MCIMX8M-EVKB-design/m-p/951882#M142285</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;As per standard any host device USB 3.0 max current consumption is 0.9A only.&lt;/P&gt;&lt;P&gt;As per schematics any specific reason to set here 2.1A even though such host device will not get connect here&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yaseen&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Sep 2019 09:31:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-MCIMX8M-EVKB-design/m-p/951882#M142285</guid>
      <dc:creator>nadira</dc:creator>
      <dc:date>2019-09-16T09:31:40Z</dc:date>
    </item>
    <item>
      <title>Re: About MCIMX8M-EVKB design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-MCIMX8M-EVKB-design/m-p/951883#M142286</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Weidong,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Any updates for previous query.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yaseen&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 01 Oct 2019 12:39:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-MCIMX8M-EVKB-design/m-p/951883#M142286</guid>
      <dc:creator>nadira</dc:creator>
      <dc:date>2019-10-01T12:39:19Z</dc:date>
    </item>
    <item>
      <title>Re: About MCIMX8M-EVKB design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-MCIMX8M-EVKB-design/m-p/951884#M142287</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;VBUS's source is from&amp;nbsp; DCDC_5V,&amp;nbsp; which means that DCDC_5V cannot provide more than 2.1A of current to USB devices, otherwise, 5V of the internal circuit may not be enough. If you want to limit VBUS to the maximum 1A current in your circuit, you can.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope this explanation will help you.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a nice day!&lt;/P&gt;&lt;P&gt;BR,&lt;/P&gt;&lt;P&gt;Weidong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 08 Oct 2019 03:55:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-MCIMX8M-EVKB-design/m-p/951884#M142287</guid>
      <dc:creator>weidong_sun</dc:creator>
      <dc:date>2019-10-08T03:55:03Z</dc:date>
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