i.MX ProcessorsのトピックRe: DDR PHY Register mapping question from Reference Manual

DDR PHY Register mapping question from Reference Manual

shangregister — Tue, 22 Oct 2019 04:06:04 GMT

Hi All

i don't know what is the DDR PHY register related to the " i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual, Rev. 2, 08/2019"

In MX8M_LPDDR4_RPA_v23.xlsx DDR Tools it represent like this ;

DDR_PHY_Dq0LnSel_0	0x3C040280	0x00000000
DDR_PHY_Dq1LnSel_0	0x3C040284	0x00000001
DDR_PHY_Dq2LnSel_0	0x3C040288	0x00000002
DDR_PHY_Dq3LnSel_0	0x3C04028C	0x00000003
DDR_PHY_Dq4LnSel_0	0x3C040290	0x00000004
DDR_PHY_Dq5LnSel_0	0x3C040294	0x00000005
DDR_PHY_Dq6LnSel_0	0x3C040298	0x00000006
DDR_PHY_Dq7LnSel_0	0x3C04029C	0x00000007

but gen from MSCALE_DDR_Tool.exe the lpddr4_timing.c it represent like this :

struct dram_cfg_param ddr_ddrphy_cfg[] = {

{0x100a0,0x0},
{0x100a1,0x1},
{0x100a2,0x2},
{0x100a3,0x3},
{0x100a4,0x4},
{0x100a5,0x5},
{0x100a6,0x6},
{0x100a7,0x7},

....

...

then in the Applications Processors Reference Manual represent like this :

DWC_DDRPHYA_DBYTE0 base address: 1_0000h

9.4.3.3.35 Maps Phy DQ lane to memory DQ0 (Dq0LnSel - Dq7LnSel)

9.4.3.3.35.1 Offset
For n = 0 to 7:
Register Offset
DqnLnSel 140h + (n × 2h)

in this moment i know

0x3C000000 from manual DDR PHY Register base addr

0x100a0 from lpddr4_timing.c

0x3C040280 from the ddr tools excel

formula in the uboot code like this 0x3C000000 + 4*0x100a0 = 0x3C040280 this is fine, i understand .

but what is the Reference Manual represent ??? DqnLnSel 140h + (n × 2h)

i don't know how to use 140h ??

how can be from 0x3C000000+DqnLnSel 140h + (n × 2h) to be a 0x3C040280 ???

Re: DDR PHY Register mapping question from Reference Manual

igorpadykov — Tue, 22 Oct 2019 09:46:31 GMT

Hi Hanson

>what is the Reference Manual represent ??? DqnLnSel 140h + (n × 2h)

Dq0LnSel Offset=140h + ((n=0) × 2h)
Dq1LnSel Offset=140h + ((n=1) × 2h)
Dq2LnSel Offset=140h + ((n=2) × 2h)
...
e.t.c.

Best regards
igor
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Re: DDR PHY Register mapping question from Reference Manual

shangregister — Wed, 23 Oct 2019 01:16:42 GMT

hi igorpadykov,

u just repeat my question.........

i know what is n for it

//============================

For n = 0 to 7:
Register Offset
DqnLnSel 140h + (n × 2h)

//============================

it is wrote on my top post.

anyway what is the 9.4.3.3.35 Maps Phy DQ lane to memory DQ0 (Dq0LnSel - Dq7LnSel) completed address??

i know the address is 0x3C040280

how can be 0x3C000000 +140h + (n=0 × 2h) to get 0x3C040280 ???

which formula can get the right answer form the menu offset(140h+(n=0 x2h))?

Re: DDR PHY Register mapping question from Reference Manual

igorpadykov — Wed, 23 Oct 2019 06:27:50 GMT

description in Manual is given from IP module description (there is "NOTE":

Synopsys Proprietary. Used with permission) as "16 bit width" while MX8M_LPDDR4_RPA_v23.xlsx

uses 32 bit addresses.

Best regards
igor

Re: DDR PHY Register mapping question from Reference Manual

shangregister — Thu, 24 Oct 2019 07:03:40 GMT

so any detail of that??

do you Synopsys PHY datasheet or the contact window??