topic Re: clock set up for a simple-audio-card in i.MX Processors

clock set up for a simple-audio-card

kapil_bhutani — Fri, 20 Sep 2019 04:30:47 GMT

I want to know a working example of DTS for sai, codec and simple-audio-card in kernel 5.0.5

using imx8mq and ti, pcm3060, specially from the clocks perspective.

I have got a sound card through the simple-audio-card, but when I try to play back a WAV file using aplay, it fails in hw_params check inside fsl_sai driver.

Here are the details.

I am working on getting simple_audio_card work for imx8mq and pcm3060 codec, I am on kernel version 5.05 and it appears both the the platform driver (fsl_sai) and the codec driver (pcm3060) support the ASOC design and the simple audio card. Here is the snapshot of my dts for simple audio card

Add pcm3060 on espi2

&ecspi2 {

fsl,spi-num-chipselects = <1>;

cs-gpios = <&gpio5 13 0>;

pinctrl-names = "default";

pinctrl-0 = <&pinctrl_ecspi2>;

status = "okay";

// As per the IMX8MDQLQRM applications processors reference manual PDF

// 7.1.4 SDMA event mapping

// NOTES:

// - our transfer sizes aren't big enough to justify DMA

// - we need a patched imx-smda.c unless we're using Linux 5.1 or newer

// dmas = <&sdma1 2 7 0>, <&sdma1 3 7 0>;

// dma-names = "rx", "tx";

pcm3060: pcm3060@0 {

#sound-dai-cells = <0>;

compatible = "pcm3060";

spi-max-frequency = <20000000>;

reg = <0>;

};

Add a new sai device

sai1: sai@30010000 {

#sound-dai-cells = <0>;

compatible = "fsl,imx8mq-sai",

"fsl,imx6sx-sai";

reg = <0x0 0x30010000 0x0 0x10000>;

interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,

<&clk IMX8MQ_CLK_SAI1_ROOT>,

<&clk IMX8MQ_AUDIO_PLL1>,

<&clk IMX8MQ_CLK_DUMMY>;

clock-names = "bus", "mclk1", "mclk2", "mclk3";

dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;

dma-names = "rx", "tx";

fsl,dataline = <0xff 0xff>;

status = "disabled";

};

Enable sai and assign clocks

&sai1 {

#sound-dai-cells = <0>;

pinctrl-names = "default";

pinctrl-0 = <&pinctrl_sai1>;

assigned-clocks = <&clk IMX8MQ_SAI1>;

assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;

assigned-clock-rates = <49152000>;

status = "okay";

};

Define sai pin controls

pinctrl_sai1: sai1grp {

fsl,pins = <

MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6

MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6

MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6

MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6

MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6

};

Define simple sound card

sound {

compatible = "simple-audio-card";

simple-audio-card,name = "pcm3060-audio";

simple-audio-card,format = "i2s";

simple-audio-card,bitclock-master = <&dai_cpu>;

simple-audio-card,frame-master = <&dai_cpu>;

simple-audio-card,widgets =

"Line", "Balanced In",

"Line", "Balanced Out",

"Line", "Unbalanced Out",

"Line", "Unbalanced In";

simple-audio-card,routing =

"INL", "Balanced In",

"INR", "Unbalanced In",

"Balanced Out", "OUTL",

"Unbalanced Out", "OUTR";

dai_cpu: simple-audio-card,cpu {

sound-dai = <&sai1>;

};

dai0-codec: simple-audio-card,codec {

sound-dai = <&pcm3060>;

clocks = <&clk IMX8MQ_CLK_SAI1_ROOT>;

};

Assign AUDIO_PLL1 to the desired frequency

&clk {

assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>;

assigned-clock-rates = <49152000>;

};

Issue

The device tree specifically the clocks for sai. This is based on what is used on upstream (5.2.x) and NXP maintained 4.19.y for i.MX8mq branch. On upstream, they provide the bus clock and only one master clock (mclk1). This configuration is not fails when I am trying to playback an audio wav file. When the sai driver tries to set the bitclock for i2s. (sound/soc/fsl/fsl_sai.c :: fsl_sai_set_bclk), the m_clck provided to the driver [as specified in the dts] does not match the requirement of the sample rate of the audio being played. Following the code snippet of that function with my addition logging.

sai1: sai@30010000 {

#sound-dai-cells = <0>;

compatible = "fsl,imx8mq-sai",

"fsl,imx6sx-sai";

reg = <0x0 0x30010000 0x0 0x10000>;

interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,

<&clk IMX8MQ_CLK_SAI1_ROOT>,

<&clk IMX8MQ_AUDIO_PLL1>,<-------------------------- On upstream it is IMX8MQ_CLK_DUMMY, I supplied AUDIO_PLL1 as one of the mclk and it does fit for the stream playback, but fails when it tries to prepare and enable that clock.

<&clk IMX8MQ_CLK_DUMMY>;

clock-names = "bus", "mclk1", "mclk2", "mclk3";

dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;

dma-names = "rx", "tx";

fsl,dataline = <0xff 0xff>;

status = "disabled";

};

&sai1 {

#sound-dai-cells = <0>;

pinctrl-names = "default";

pinctrl-0 = <&pinctrl_sai1>;

assigned-clocks = <&clk IMX8MQ_SAI1>;

assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;

assigned-clock-rates = <49152000>;

status = "okay";

};

&clk {

assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>;

assigned-clock-rates = <49152003>;

};

I get following logs

2018-03-09T12:39:49.515972+00:00 localhost kernel: [ 336.690525] 001: fsl-sai 30010000.sai: inside fsl_sai_hw_params channels=2 word_width=24 slots=2 slot_width=24

2018-03-09T12:39:49.516023+00:00 localhost kernel: [ 336.690545] 001: fsl-sai 30010000.sai: inside fsl_sai_set_bclk for freq: 768000Hz

2018-03-09T12:39:49.516028+00:00 localhost kernel: [ 336.690554] 001: fsl-sai 30010000.sai: failed to get the required clock rate 12500000Hz for frequency: 768000Hz ----> bus

2018-03-09T12:39:49.516032+00:00 localhost kernel: [ 336.690563] 001: fsl-sai 30010000.sai: failed to get the required clock rate 25000000Hz for frequency: 768000Hz -----> mclk1 --- > SAI1_ROOT

2018-03-09T12:39:49.516036+00:00 localhost kernel: [ 336.690571] 001: fsl-sai 30010000.sai: ratio 64 for freq 768000Hz based on clock 49152001Hz -----------------------------------------> mclk2 ---> AUDIO_PLL1 ----> it is configured to run at a desirable rate, but fails when the driver tries to prepare and enable the clock.

2018-03-09T12:39:49.516039+00:00 localhost kernel: [ 336.690579] 001: fsl-sai 30010000.sai: failed to get the clock 0Hz for frequency: 768000Hz

2018-03-09T12:39:49.516046+00:00 localhost kernel: [ 336.690602] 001: fsl-sai 30010000.sai: best fit: clock id=2, div=32, deviation =1

2018-03-09T12:39:49.516050+00:00 localhost kernel: [ 336.700617] 001: fsl-sai 30010000.sai: inside fsl_sai_hw_params could not prepare clk with clock id: 2

2018-03-09T12:39:49.526003+00:00 localhost kernel: [ 336.701229] 001: fsl-sai 30010000.sai: ASoC: can't set 30010000.sai hw params: -110

Can you please tell me that how were the clock arrangements in you device tree when you made it work with simple audio card

Cheers

Re: clock set up for a simple-audio-card

igorpadykov — Fri, 20 Sep 2019 10:00:14 GMT

Hi Kapil

one can look at example on

SAI on i.MX8M Mini

Note, kernel 5.0.5 is not supported by nxp, official supported kernels are described on

Linux documentation
i.MX Software | NXP

linux-imx - i.MX Linux kernel

Best regards
igor
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Re: clock set up for a simple-audio-card

remingtonfurman — Sat, 21 Sep 2019 15:22:03 GMT

What's the output of this command?

cat /sys/kernel/debug/clk/clk_summary

That's a quick way to make sure that the clock chain from the master oscillator down to the SAI peripheral is correct at run time. The Linux clk driver framework tries to automatically derive the hardware PLL and divider settings, but it often does the wrong thing until you specify the right settings in the device tree. Try to work backwards through the whole chain. You'll have to spend a lot of time with the clock chapters of the iMX8 reference manual and the clk framework documentation. Depending on your kernel version it's at Documentation/clk.txt or Documentation/driver-api/clk.rst. A nicely formatted version is here: The Common Clk Framework — The Linux Kernel documentation

I'm not familiar with the iMX8, but I have used the iMX6. Your target for the input clock frequency to the SAI peripheral looks okay. It's two times the value I used (24576000), so it could be used to generate I2S SCK frequencies for multiples of 8000kHz stereo sample rates. One thing that is missing from the iMX6 reference manual is the maximum input frequency for the ESAI, so I had to guess. 24.6MHz worked for me, but maybe 49.2MHz is too high?

I tried to show my work in this post, so maybe it's helpful to you even though the hardware is different:
https://community.nxp.com/message/1169193?commentID=1169193

Re: clock set up for a simple-audio-card

kapil_bhutani — Mon, 23 Sep 2019 00:00:32 GMT

Thanks Igor,

I can see that it is not yet the supported Kernel from NXP.

But in another reply recently you mentioned that simple audio card is not supported with 4.14

Problem with SGTL5000 audio codec and Simple Audio Card driver on i.MX8MM

I wanted to use simple audio card for my use case with ALSA, and what I could see in the later versions of the kernel (5.0.5 and above), there are examples in the imx8mq DTS and DTSI.

My question was more fundamental, that what could prevent enabling the PLL clock in imx8mq.

Even if we do not go via the simple audio card way, what should be mclks provided to sai and what should be the parents of that clock.

Here is the dump of my clock tree? should I connect them differently? Would support of (imx) clock enable be missing from the 5.05?

---------------------------------------------------------------------------------------------
dummy 0 0 0 0 0 0 50000
clk_ext4 0 0 0 133000000 0 0 50000
clk_ext3 0 0 0 133000000 0 0 50000
clk_ext2 0 0 0 133000000 0 0 50000
clk_ext1 0 0 0 133000000 0 0 50000
osc_27m 0 0 0 27000000 0 0 50000
osc_25m 9 12 0 25000000 0 0 50000
...............
other clocks
...............
audio_pll1_ref_sel 0 0 0 25000000 0 0 50000
audio_pll1_bypass 0 0 0 25000000 0 0 50000
audio_pll1_out 0 0 0 25000000 0 0 50000
sai1 0 0 0 25000000 0 0 50000
sai1_root_clk 0 0 0 25000000 0 0 50000
audio_pll1_ref_div 0 0 0 5000000 0 0 50000
audio_pll1 0 0 0 49152001 0 0 50000
ckil 0 0 0 32768 0 0 50000

Re: clock set up for a simple-audio-card

kapil_bhutani — Mon, 23 Sep 2019 04:41:05 GMT

Thanks Remington.

I ll go through the documentation.

This is how my device tree looks like

sai1: sai@30010000 {

#sound-dai-cells = <0>;

compatible = "fsl,imx8mq-sai",

"fsl,imx6sx-sai";

reg = <0x0 0x30010000 0x0 0x10000>;

interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,

<&clk IMX8MQ_CLK_SAI1_ROOT>,

<&clk IMX8MQ_AUDIO_PLL1>,<-------------------------- On upstream it is IMX8MQ_CLK_DUMMY, I supplied AUDIO_PLL1 as one of the mclck and it does fit for the stream playback, but fails when it tries to prepare and enable that clock.

<&clk IMX8MQ_CLK_DUMMY>;

clock-names = "bus", "mclk1", "mclk2", "mclk3";

dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;

dma-names = "rx", "tx";

fsl,dataline = <0xff 0xff>;

status = "disabled";

};

&sai1 {

#sound-dai-cells = <0>;

pinctrl-names = "default";

pinctrl-0 = <&pinctrl_sai1>;

assigned-clocks = <&clk IMX8MQ_SAI1>;

assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;

assigned-clock-rates = <49152000>;

status = "okay";

};

&clk {

assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>;

assigned-clock-rates = <49152003>;

};

Here is the clock summary

As you can see, though I have configured SAI1 to run at 49152000 and derive from IMX8MQ_AUDIO_PLL1_OUT, which should derive from IMX8MQ_AUDIO_PLL1 configured to run at 49152003.

But on the board, when I dump the clock summary, SAI is configured to run on 25 MHz.

enable prepare protect duty

clock count count count rate accuracy phase cycle

---------------------------------------------------------------------------------------------

dummy 0 0 0 0 0 0 50000

clk_ext4 0 0 0 133000000 0 0 50000

clk_ext3 0 0 0 133000000 0 0 50000

clk_ext2 0 0 0 133000000 0 0 50000

clk_ext1 0 0 0 133000000 0 0 50000

osc_27m 0 0 0 27000000 0 0 50000

osc_25m 9 12 0 25000000 0 0 50000

gpt_3m 0 0 0 3125000 0 0 50000

pcie2_aux 0 0 0 25000000 0 0 50000

pcie2_phy 0 0 0 25000000 0 0 50000

pcie2_ctrl 0 0 0 25000000 0 0 50000

pcie2_root_clk 0 0 0 25000000 0 0 50000

csi2_esc 0 0 0 25000000 0 0 50000

csi2_phy_ref 0 0 0 25000000 0 0 50000

csi2_core 0 0 0 25000000 0 0 50000

csi2_root_clk 0 0 0 25000000 0 0 50000

csi1_esc 0 0 0 25000000 0 0 50000

csi1_phy_ref 0 0 0 25000000 0 0 50000

csi1_core 0 0 0 25000000 0 0 50000

csi1_root_clk 0 0 0 25000000 0 0 50000

dsi_ahb 0 0 0 25000000 0 0 50000

dsi_esc 0 0 0 25000000 0 0 50000

dsi_dbi 0 0 0 25000000 0 0 50000

dsi_phy_ref 0 0 0 25000000 0 0 50000

dsi_core 0 0 0 25000000 0 0 50000

clko2 0 0 0 25000000 0 0 50000

wdog 1 1 0 25000000 0 0 50000

wdog3_root_clk 0 0 0 25000000 0 0 50000

wdog2_root_clk 0 0 0 25000000 0 0 50000

wdog1_root_clk 1 1 0 25000000 0 0 50000

gpt1 0 0 0 25000000 0 0 50000

gpt1_root_clk 0 0 0 25000000 0 0 50000

pwm4 0 0 0 25000000 0 0 50000

pwm4_root_clk 0 0 0 25000000 0 0 50000

pwm3 0 0 0 25000000 0 0 50000

pwm3_root_clk 0 0 0 25000000 0 0 50000

pwm2 0 0 0 25000000 0 0 50000

pwm2_root_clk 0 0 0 25000000 0 0 50000

pwm1 0 0 0 25000000 0 0 50000

pwm1_root_clk 0 0 0 25000000 0 0 50000

uart4 0 0 0 25000000 0 0 50000

uart4_root_clk 0 0 0 25000000 0 0 50000

uart3 0 0 0 25000000 0 0 50000

uart3_root_clk 0 0 0 25000000 0 0 50000

uart2 0 0 0 25000000 0 0 50000

uart2_root_clk 0 0 0 25000000 0 0 50000

uart1 1 1 0 25000000 0 0 50000

uart1_root_clk 2 4 0 25000000 0 0 50000

i2c4 0 1 0 25000000 0 0 50000

i2c4_root_clk 0 1 0 25000000 0 0 50000

i2c3 0 0 0 25000000 0 0 50000

i2c3_root_clk 0 0 0 25000000 0 0 50000

i2c2 0 1 0 25000000 0 0 50000

i2c2_root_clk 0 1 0 25000000 0 0 50000

i2c1 1 1 0 25000000 0 0 50000

i2c1_root_clk 1 1 0 25000000 0 0 50000

enet_phy 1 1 0 25000000 0 0 50000

spdif2 0 0 0 25000000 0 0 50000

spdif1 0 0 0 25000000 0 0 50000

sai6 0 0 0 25000000 0 0 50000

sai6_root_clk 0 0 0 25000000 0 0 50000

sai5 0 0 0 25000000 0 0 50000

sai5_root_clk 0 0 0 25000000 0 0 50000

sai4 0 0 0 25000000 0 0 50000

sai4_root_clk 0 0 0 25000000 0 0 50000

sai3 0 0 0 25000000 0 0 50000

sai3_root_clk 0 0 0 25000000 0 0 50000

sai2 0 0 0 25000000 0 0 50000

sai2_root_clk 0 0 0 25000000 0 0 50000

lcdif_pixel 0 0 0 25000000 0 0 50000

dc_pixel 0 0 0 25000000 0 0 50000

pcie1_aux 0 0 0 25000000 0 0 50000

pcie1_phy 0 0 0 25000000 0 0 50000

pcie1_ctrl 0 0 0 25000000 0 0 50000

pcie1_root_clk 0 0 0 25000000 0 0 50000

disp_dc8000 0 0 0 25000000 0 0 50000

disp_root_clk 0 0 0 25000000 0 0 50000

disp_dtrc 0 0 0 25000000 0 0 50000

vpu_g2 0 0 0 25000000 0 0 50000

vpu_g2_root_clk 0 0 0 25000000 0 0 50000

vpu_g1 0 0 0 25000000 0 0 50000

vpu_g1_root_clk 0 0 0 25000000 0 0 50000

audio_ahb 0 1 0 25000000 0 0 50000

ipg_audio_root 0 1 0 12500000 0 0 50000

sdma2_clk 0 0 0 12500000 0 0 50000

sai6_ipg_clk 0 0 0 12500000 0 0 50000

sai5_ipg_clk 0 0 0 12500000 0 0 50000

sai4_ipg_clk 0 0 0 12500000 0 0 50000

sai1_ipg_clk 0 1 0 12500000 0 0 50000

noc_apb 1 1 0 25000000 0 0 50000

gpu_ahb 0 0 0 25000000 0 0 50000

gpu_axi 0 0 0 25000000 0 0 50000

vpu_bus 0 0 0 25000000 0 0 50000

vpu_dec_root_clk 0 0 0 25000000 0 0 50000

gpu_shader_src 0 0 0 25000000 0 0 50000

gpu_shader_cg 0 0 0 25000000 0 0 50000

gpu_shader_div 0 0 0 25000000 0 0 50000

gpu_core_src 0 0 0 25000000 0 0 50000

gpu_core_cg 0 0 0 25000000 0 0 50000

gpu_core_div 0 0 0 25000000 0 0 50000

gpu_root_clk 0 0 0 25000000 0 0 50000

dram_pll1_ref_sel 1 1 0 25000000 0 0 50000

dram_pll1_ref_div 1 1 0 25000000 0 0 50000

dram_pll1 1 1 0 2000000000 0 0 50000

dram_pll1_out 1 1 0 2000000000 0 0 50000

dram_pll1_out_div 1 1 0 66666667 0 0 50000

dram_pll2 1 1 0 800000000 0 0 50000

dram_pll2_div 1 1 0 800000000 0 0 50000

dram_pll2_out 1 1 0 800000000 0 0 50000

dram_pll_out 1 1 0 800000000 0 0 50000

dram_core_clk 1 1 0 800000000 0 0 50000

sys3_pll1_ref_sel 0 0 0 25000000 0 0 50000

sys3_pll1_out 0 0 0 25000000 0 0 50000

sys3_pll1_out_div 0 0 0 1041667 0 0 50000

sys3_pll2 0 0 0 1000000000 0 0 50000

sys3_pll2_div 0 0 0 1000000000 0 0 50000

sys3_pll1_ref_div 0 0 0 25000000 0 0 50000

sys3_pll1 0 0 0 1600000000 0 0 50000

sys2_pll1_ref_sel 1 1 0 25000000 0 0 50000

sys3_pll2_out 0 0 0 25000000 0 0 50000

sys3_pll_out 0 0 0 25000000 0 0 50000

sys2_pll1_ref_div 1 1 0 25000000 0 0 50000

sys2_pll1 1 1 0 1600000000 0 0 50000

sys2_pll1_out 1 1 0 1600000000 0 0 50000

sys2_pll1_out_div 1 1 0 66666667 0 0 50000

sys2_pll2 1 1 0 1000000000 0 0 50000

sys2_pll2_div 1 1 0 1000000000 0 0 50000

sys2_pll2_out 1 1 0 1000000000 0 0 50000

sys2_pll_out 3 4 0 1000000000 0 0 50000

sys2_pll_1000m 0 0 0 1000000000 0 0 50000

sys2_pll_500m 0 0 0 500000000 0 0 50000

usb_bus 0 0 0 500000000 0 0 50000

sys2_pll_333m 1 1 0 333333333 0 0 50000

main_axi 1 1 0 333333333 0 0 50000

sys2_pll_250m 0 0 0 250000000 0 0 50000

dram_alt 0 0 0 250000000 0 0 50000

dram_alt_root 0 0 0 62500000 0 0 50000

sys2_pll_200m 0 2 0 200000000 0 0 50000

ecspi3 0 0 0 200000000 0 0 50000

ecspi3_root_clk 0 0 0 200000000 0 0 50000

ecspi2 0 1 0 200000000 0 0 50000

ecspi2_root_clk 0 2 0 200000000 0 0 50000

ecspi1 0 1 0 200000000 0 0 50000

ecspi1_root_clk 0 2 0 200000000 0 0 50000

sys2_pll_166m 0 0 0 166666666 0 0 50000

sys2_pll_125m 1 1 0 125000000 0 0 50000

enet_ref 1 1 0 125000000 0 0 50000

sys2_pll_100m 1 1 0 100000000 0 0 50000

enet_timer 1 1 0 25000000 0 0 50000

sys2_pll_50m 0 0 0 50000000 0 0 50000

sys1_pll1_ref_sel 1 1 0 25000000 0 0 50000

sys1_pll1_ref_div 1 1 0 25000000 0 0 50000

sys1_pll1 1 1 0 1600000000 0 0 50000

sys1_pll1_out 1 1 0 1600000000 0 0 50000

sys1_pll1_out_div 1 1 0 66666667 0 0 50000

sys1_pll2 1 1 0 800000000 0 0 50000

sys1_pll2_div 1 1 0 800000000 0 0 50000

sys1_pll2_out 1 1 0 800000000 0 0 50000

sys1_pll_out 3 3 0 800000000 0 0 50000

sys1_pll_800m 2 2 0 800000000 0 0 50000

dram_apb 1 1 0 200000000 0 0 50000

noc 1 1 0 400000000 0 0 50000

disp_rtrm 0 0 0 400000000 0 0 50000

disp_rtrm_root_clk 0 0 0 400000000 0 0 50000

disp_apb 0 0 0 133333334 0 0 50000

disp_apb_root_clk 0 0 0 133333334 0 0 50000

disp_axi 0 0 0 800000000 0 0 50000

disp_axi_root_clk 0 0 0 800000000 0 0 50000

sys1_pll_400m 0 0 0 400000000 0 0 50000

usdhc2 0 0 0 200000000 0 0 50000

usdhc2_root_clk 0 0 0 200000000 0 0 50000

usdhc1 0 0 0 400000000 0 0 50000

usdhc1_root_clk 0 0 0 400000000 0 0 50000

nand 0 0 0 100000000 0 0 50000

nand_root_clk 0 0 0 100000000 0 0 50000

sys1_pll_266m 1 1 0 266666666 0 0 50000

nand_usdhc_bus 0 0 0 266666666 0 0 50000

nand_usdhc_rawnand_clk 0 0 0 266666666 0 0 50000

enet_axi 1 1 0 266666666 0 0 50000

enet1_root_clk 2 2 0 266666666 0 0 50000

sys1_pll_200m 0 0 0 200000000 0 0 50000

sys1_pll_160m 0 0 0 160000000 0 0 50000

sys1_pll_133m 1 1 0 133333333 0 0 50000

ahb 1 1 0 133333333 0 0 50000

ipg_root 2 2 0 66666667 0 0 50000

sdma1_clk 4 2 0 66666667 0 0 50000

tmu_root_clk 1 1 0 66666667 0 0 50000

sai3_ipg_clk 0 0 0 66666667 0 0 50000

sai2_ipg_clk 0 0 0 66666667 0 0 50000

ocotp_root_clk 0 0 0 66666667 0 0 50000

mu_root_clk 0 0 0 66666667 0 0 50000

sys1_pll_100m 0 0 0 100000000 0 0 50000

usb_phy_ref 0 0 0 100000000 0 0 50000

usb2_phy_root_clk 0 0 0 100000000 0 0 50000

usb1_phy_root_clk 0 0 0 100000000 0 0 50000

usb_core_ref 0 0 0 100000000 0 0 50000

usb2_ctrl_root_clk 0 0 0 100000000 0 0 50000

usb1_ctrl_root_clk 0 0 0 100000000 0 0 50000

qspi 0 0 0 100000000 0 0 50000

qspi_root_clk 0 0 0 100000000 0 0 50000

sys1_pll_80m 0 0 0 80000000 0 0 50000

sys1_pll_40m 0 0 0 40000000 0 0 50000

wrclk 0 0 0 40000000 0 0 50000

video_pll1_ref_sel 0 0 0 25000000 0 0 50000

video_pll1_bypass 0 0 0 25000000 0 0 50000

video_pll1_out 0 0 0 25000000 0 0 50000

video_pll1_ref_div 0 0 0 5000000 0 0 50000

video_pll1 0 0 0 650000000 0 0 50000

audio_pll2_ref_sel 0 0 0 25000000 0 0 50000

audio_pll2_bypass 0 0 0 25000000 0 0 50000

audio_pll2_out 0 0 0 25000000 0 0 50000

audio_pll2_ref_div 0 0 0 5000000 0 0 50000

audio_pll2 0 0 0 650000000 0 0 50000

audio_pll1_ref_sel 0 0 0 25000000 0 0 50000

audio_pll1_bypass 0 0 0 25000000 0 0 50000

audio_pll1_out 0 0 0 25000000 0 0 50000

sai1 0 0 0 25000000 0 0 50000

sai1_root_clk 0 0 0 25000000 0 0 50000

audio_pll1_ref_div 0 0 0 5000000 0 0 50000

audio_pll1 0 0 0 49152001 0 0 50000

vpu_pll_ref_sel 0 0 0 25000000 0 0 50000

vpu_pll_bypass 0 0 0 25000000 0 0 50000

vpu_pll_out 0 0 0 25000000 0 0 50000

vpu_pll_ref_div 0 0 0 5000000 0 0 50000

vpu_pll 0 0 0 600000000 0 0 50000

gpu_pll_ref_sel 0 0 0 25000000 0 0 50000

gpu_pll_bypass 0 0 0 25000000 0 0 50000

gpu_pll_out 0 0 0 25000000 0 0 50000

gpu_pll_ref_div 0 0 0 5000000 0 0 50000

gpu_pll 0 0 0 800000000 0 0 50000

arm_pll_ref_sel 1 1 0 25000000 0 0 50000

arm_pll_ref_div 1 1 0 5000000 0 0 50000

arm_pll 1 1 0 1000000000 0 0 50000

arm_pll_bypass 1 1 0 1000000000 0 0 50000

arm_pll_out 1 1 0 1000000000 0 0 50000

vpu_src 0 0 0 1000000000 0 0 50000

vpu_cg 0 0 0 1000000000 0 0 50000

vpu_div 0 0 0 1000000000 0 0 50000

arm_a53_src 1 1 0 1000000000 0 0 50000

arm_a53_cg 1 1 0 1000000000 0 0 50000

arm_a53_div 0 0 0 1000000000 0 0 50000

ckil 0 0 0 32768 0 0 50000

root@localhost:~#

Re: clock set up for a simple-audio-card

triedgetech — Mon, 25 Apr 2022 08:28:44 GMT

Hey dude, did you figure it out?

topic Re: clock set up for a simple-audio-card in i.MX Processors

clock set up for a simple-audio-card

Add pcm3060 on espi2

Add a new sai device

Enable sai and assign clocks

Define sai pin controls

Define simple sound card

Assign AUDIO_PLL1 to the desired frequency

Issue

Re: clock set up for a simple-audio-card

Re: clock set up for a simple-audio-card

Re: clock set up for a simple-audio-card

Re: clock set up for a simple-audio-card

Re: clock set up for a simple-audio-card