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    <title>i.MX ProcessorsのトピックRe: Maximum SPI throughput over imx6q</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Maximum-SPI-throughput-over-imx6q/m-p/946967#M141639</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Nilesh&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;you are right, overhead is introduced by operating system and internal&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;bus latencies. In particular by NIC-301 described in Chapter 45&lt;BR /&gt;Network Interconnect Bus System (NIC-301) i.MX6Q Reference Manual and&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;its latencies in sect.3.2 NIC-301 AN4947&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/application-note/AN4947.pdf" title="https://www.nxp.com/docs/en/application-note/AN4947.pdf"&gt;https://www.nxp.com/docs/en/application-note/AN4947.pdf&lt;/A&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 19 Sep 2019 10:24:22 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2019-09-19T10:24:22Z</dc:date>
    <item>
      <title>Maximum SPI throughput over imx6q</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Maximum-SPI-throughput-over-imx6q/m-p/946966#M141638</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;I am using custom board based on IMX6Q with below environment,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Linux Kernel : 3.14.38&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;ADC : ADS8568(TI)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Number of ADC : 4&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;TI ADC is interfaced with IMX6Q as per below,&lt;/SPAN&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;SPAN style="color: #333333; background-color: #ffffff;"&gt;Common Conversion pulse given to all ADCs using GPIO.&lt;/SPAN&gt;&lt;/LI&gt;&lt;LI&gt;Individual chip select pin for each ADC.&lt;/LI&gt;&lt;LI&gt;Individual SPI for each ADC.&lt;/LI&gt;&lt;LI&gt;SPI operating frequency is 30Mhz freq and 32 bits per word.&lt;/LI&gt;&lt;LI&gt;ADCs are configured in software mode.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Our Application is to fetch the data from&lt;/SPAN&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&amp;nbsp;4 ADCs simultaneously, each has 8-channels, for a total of 32 channels of data.On HIGH transition of conversion pulse, read 16-bytes of data from single ADC and&amp;nbsp;&lt;SPAN&gt;after reading, conversion pulse becomes LOW. So, frequency of the CONVST will be the sampling frequency.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;To do that we set&amp;nbsp;HIGH common CONVST(conversion start) signal to 4 ADCs using GPIO. Then We read 4 ADCs using four different SPI sequentially in the chunks of 16 bytes. Then LOW the GPIO which is common across the all ADCs.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;Our observation when reading data from single ADC, time duration is 50-60 microseconds. Also,&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;when reading data from the 4 ADCs, time duration is 225- 240 microseconds. We have also check it with the 50Mhz SCLK and the data show no major difference.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="background-color: #ffffff; color: #51626f; "&gt;Our goal is to fetch 4 ADCs data within 33us. which will give 30KSPS rate of sampling. If IMX6Q SPI have good&amp;nbsp;throughput&amp;nbsp;then it&amp;nbsp;should be&amp;nbsp;achieve&amp;nbsp;by 30MHZ SCLK.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;Is that a overhead of LINUX or anything else ? DMA won't be enable in this case as it enable beyond the 64 Bytes as per the spi-imx.c driver.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;Are we missing something or is there any solution to achieve this ?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 19 Sep 2019 09:07:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Maximum-SPI-throughput-over-imx6q/m-p/946966#M141638</guid>
      <dc:creator>nilesh_patel</dc:creator>
      <dc:date>2019-09-19T09:07:10Z</dc:date>
    </item>
    <item>
      <title>Re: Maximum SPI throughput over imx6q</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Maximum-SPI-throughput-over-imx6q/m-p/946967#M141639</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Nilesh&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;you are right, overhead is introduced by operating system and internal&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;bus latencies. In particular by NIC-301 described in Chapter 45&lt;BR /&gt;Network Interconnect Bus System (NIC-301) i.MX6Q Reference Manual and&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;its latencies in sect.3.2 NIC-301 AN4947&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/application-note/AN4947.pdf" title="https://www.nxp.com/docs/en/application-note/AN4947.pdf"&gt;https://www.nxp.com/docs/en/application-note/AN4947.pdf&lt;/A&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 19 Sep 2019 10:24:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Maximum-SPI-throughput-over-imx6q/m-p/946967#M141639</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-09-19T10:24:22Z</dc:date>
    </item>
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