Refresh cycle counter in IPU

Kazuma_Sasaki — Wed, 19 Jun 2019 13:15:35 GMT

From i.MX 6Solo/6DualLite Applications Processor Reference Manual, Rev. 4, 07/2018

38.1.2.1.6.1 Screen Refresh
• The refresh rate may vary within a predefined range. Within this range, the rate is
dynamically adjusted to the content update rate.
• An indication about the availability of new content is obtained as follows:
• If the page-flip double buffering is used, the mechanism provides this indication
• If only a single buffer is used (and incrementally updated), the IPU can receive
an indication of a modification from the ARM platform (by setting an internal
flag).
• The IPU counts the refresh cycles: the total and those with new content. The ARM
platform can use these counters to optimize display management (e.g. switching
display buffer compression on/off). The counters are reset by the ARM platform.
• The transferred data may be processed on the way, using the IC and DP.

IPU is counting display refresh cycles according to above description.

I would like to check this counter for debugging our system.

Could you please teach me register name to get the counted value?

Best Regards,

Kazuma Sasaki.

Re: Refresh cycle counter in IPU

gusarambula — Tue, 02 Jul 2019 19:38:13 GMT

Hello Kazuma Sasaki,

I made some research and the counter for refresh cycles is not accessible as it is part of the DP (Display Processor) and there is not a register from where this value could be read.

My apologies for the inconvenience.

Regards,

Re: Refresh cycle counter in IPU

Kazuma_Sasaki — Wed, 03 Jul 2019 12:52:10 GMT

Hello gusarambula,

Okay, I got it. Thank you for your support.

Best Regards,

Kazuma Sasaki.

topic Re: Refresh cycle counter in IPU in i.MX Processors

Refresh cycle counter in IPU

Re: Refresh cycle counter in IPU

Re: Refresh cycle counter in IPU