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    <title>i.MX ProcessorsのトピックRe: About interrupts</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/About-interrupts/m-p/942250#M140966</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Goto&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Is it possible to check the interrupt status with GPIO interrupt status register (GPIOx_ISR) for both Active HIGH &amp;gt;Interrupt from INT7 from GPIO and Combined interrupt indication for GPIO1 signal 0 throughout 15?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Is Active HIGH Interrupt from INT7 from GPIO's Active HIGH high-level sensitive, not rising-edge sensitive?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&amp;gt;Is Active HIGH Interrupt from INT7 from GPIO enabled by GPIO interrupt mask register (GPIOx_IMR)?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Interrupt is configured using GPIOx_ICR1, in the same way as for other interrupts (for example Combined interrupt).&lt;/P&gt;&lt;P&gt;It can be masked by GPIOx_IMR.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 20 Aug 2019 23:44:58 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2019-08-20T23:44:58Z</dc:date>
    <item>
      <title>About interrupts</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-interrupts/m-p/942249#M140965</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Hello,community&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Is it possible to check the interrupt status with GPIO interrupt status register (GPIOx_ISR) for both Active HIGH Interrupt from INT7 from GPIO and Combined interrupt indication for GPIO1 signal 0 throughout 15?&lt;BR /&gt;Is Active HIGH Interrupt from INT7 from GPIO's Active HIGH high-level sensitive, not rising-edge sensitive?&lt;BR /&gt;Is Active HIGH Interrupt from INT7 from GPIO enabled by GPIO interrupt mask register (GPIOx_IMR)?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;Best Regards, Goto&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 20 Aug 2019 10:51:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-interrupts/m-p/942249#M140965</guid>
      <dc:creator>goto11</dc:creator>
      <dc:date>2019-08-20T10:51:13Z</dc:date>
    </item>
    <item>
      <title>Re: About interrupts</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-interrupts/m-p/942250#M140966</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Goto&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Is it possible to check the interrupt status with GPIO interrupt status register (GPIOx_ISR) for both Active HIGH &amp;gt;Interrupt from INT7 from GPIO and Combined interrupt indication for GPIO1 signal 0 throughout 15?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Is Active HIGH Interrupt from INT7 from GPIO's Active HIGH high-level sensitive, not rising-edge sensitive?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&amp;gt;Is Active HIGH Interrupt from INT7 from GPIO enabled by GPIO interrupt mask register (GPIOx_IMR)?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Interrupt is configured using GPIOx_ICR1, in the same way as for other interrupts (for example Combined interrupt).&lt;/P&gt;&lt;P&gt;It can be masked by GPIOx_IMR.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 20 Aug 2019 23:44:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-interrupts/m-p/942250#M140966</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-08-20T23:44:58Z</dc:date>
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