<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: LPDDR4 settings for iMX8M</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-settings-for-iMX8M/m-p/937934#M140500</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;SPAN style="color: #3d3d3d; font-size: 11.0pt;"&gt;Anirudha&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for new board or memory it is necessary to follow steps described in&lt;/P&gt;&lt;P&gt;Chapter 4 How to bring up a new MX8MSCALE board MSCALE_DDR_Tool_User_Guide.pdf&lt;/P&gt;&lt;P&gt;included in package&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-340179"&gt;i.MX8 MSCALE SERIES DDR Tool Release (V2.10)&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;use latest uboot&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/imx8mq_evk?h=imx_v2018.03_4.14.98_2.1.0" title="https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/imx8mq_evk?h=imx_v2018.03_4.14.98_2.1.0"&gt;imx8mq_evk\freescale\board - uboot-imx - i.MX U-Boot&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 17 Sep 2019 23:24:21 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2019-09-17T23:24:21Z</dc:date>
    <item>
      <title>LPDDR4 settings for iMX8M</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-settings-for-iMX8M/m-p/937933#M140499</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We have changed LPDDR4 part from&amp;nbsp;MT53B512M32D2NP-062 WT:D to&amp;nbsp;MT53D512M32D2DS-053 WT for iMX8M design.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are getting below error log.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;U-Boot SPL 2018.03-imx_v2018.03_4.14.78_1.0.0_ga+g11b4e6e (Jun 18 2019 - 08:18:38 +0000)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;PMIC:&amp;nbsp; PFUZE100 ID=0x10&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_imem code&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_imem code pass&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_dmem code&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_dmem code pass&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Training FAILED&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Training FAILED&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_imem code&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_imem code pass&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_dmem code&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_dmem code pass&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Training FAILED&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Normal Boot&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Trying to boot from MMC2&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;MMC Device 1 not found&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;spl: could not find mmc device. error: -19&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;SPL: failed to boot from all boot devices&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;### ERROR ### Please RESET the board ###&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;U-Boot SPL 2018.03-imx_v2018.03_4.14.78_1.0.0_ga+g11b4e6e (Jun 18 2019 - 08:18:38 +0000)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;PMIC:&amp;nbsp; PFUZE100 ID=0x10&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_imem code&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_imem code pass&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_dmem code&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_dmem code pass&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Training FAILED&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Training FAILED&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_imem code&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_imem code pass&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_dmem code&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_dmem code pass&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Training FAILED&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Normal Boot&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Trying to boot from MMC2&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;U-Boot SPL 2018.03-imx_v2018.03_4.14.78_1.0.0_ga+g11b4e6e (Jun 18 2019 - 08:18:38 +0000)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;PMIC:&amp;nbsp; PFUZE100 ID=0x10&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_imem code&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_imem code pass&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_dmem code&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_dmem code pass&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Training FAILED&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Training FAILED&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_imem code&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_imem code pass&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_dmem code&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;check ddr4_pmu_train_dmem code pass&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Training FAILED&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Normal Boot&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;Trying to boot from MMC2&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;MMC Device 1 not found&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;spl: could not find mmc device. error: -19&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;SPL: failed to boot from all boot devices&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: #1f497d;"&gt;### ERROR ### Please RESET the board ###&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-size: 11.0pt; "&gt;Can you share LPDDR4 settings with the new part as we suspect the LPDDR4 settings only.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-size: 11.0pt; "&gt;We are trying the DDRtool in parallel for configurations but it would be helpful if you can share the settings for this as this new part is supported for iMX8M.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-size: 11.0pt; "&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-size: 11.0pt; "&gt;Anirudha&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 17 Sep 2019 14:11:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-settings-for-iMX8M/m-p/937933#M140499</guid>
      <dc:creator>ani10c89</dc:creator>
      <dc:date>2019-09-17T14:11:49Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR4 settings for iMX8M</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-settings-for-iMX8M/m-p/937934#M140500</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;SPAN style="color: #3d3d3d; font-size: 11.0pt;"&gt;Anirudha&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for new board or memory it is necessary to follow steps described in&lt;/P&gt;&lt;P&gt;Chapter 4 How to bring up a new MX8MSCALE board MSCALE_DDR_Tool_User_Guide.pdf&lt;/P&gt;&lt;P&gt;included in package&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-340179"&gt;i.MX8 MSCALE SERIES DDR Tool Release (V2.10)&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;use latest uboot&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/imx8mq_evk?h=imx_v2018.03_4.14.98_2.1.0" title="https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/imx8mq_evk?h=imx_v2018.03_4.14.98_2.1.0"&gt;imx8mq_evk\freescale\board - uboot-imx - i.MX U-Boot&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 17 Sep 2019 23:24:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-settings-for-iMX8M/m-p/937934#M140500</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-09-17T23:24:21Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR4 settings for iMX8M</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-settings-for-iMX8M/m-p/937935#M140501</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for response.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can you please confirm if&amp;nbsp;MT53D1024M32D4DT-053 WT:D is tested with iMX8M and the quad die is not issue.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Anirudha&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 20 Sep 2019 16:45:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-settings-for-iMX8M/m-p/937935#M140501</guid>
      <dc:creator>ani10c89</dc:creator>
      <dc:date>2019-09-20T16:45:46Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR4 settings for iMX8M</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-settings-for-iMX8M/m-p/937936#M140502</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;yes it is recommended for usage:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 20 Sep 2019 23:31:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-settings-for-iMX8M/m-p/937936#M140502</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-09-20T23:31:16Z</dc:date>
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  </channel>
</rss>

