topic i.MX6 failed DRAM address decode in i.MX Processors

i.MX6 failed DRAM address decode

Kazuma_Sasaki — Thu, 01 Aug 2019 01:27:06 GMT

Hi,

We are making a product with i.MX6S. However, In rare case, we are encountering DDR accessing error.
therefore, we would like to identify failing point in DRAM chip for quality point of view.

It is need the failed address convert to ROW-COLUMN-BANK.

According to description from table 45-5 in reference manual rev 4, 07/2018.

Accessing address is able to decode by following mapping table.

If we encountered access error at 0x12001240, we can identify failing point as following table. Is it right?

Here is our error log getting from DDR stress test tool.

============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 32, bank num: 8
Row size: 13, col size: 10
Chip select CSD0 is used
Density per chip select: 256MB
============================================
DDR Stress Test Iteration 1
Current Temperature: 46
============================================
DDR Freq: 396 MHz
t0.1: data is addr test
Address of failure(step2): 0x12001240
Data was: 0x52001240
But pattern should match address
Error: failed to run stress test!!!

Best Regards,

Kazuma Sasaki.

Re: i.MX6 failed DRAM address decode

igorpadykov — Thu, 01 Aug 2019 04:58:16 GMT

Hi Kazuma

>If we encountered access error at 0x12001240, we can identify failing point as following table. Is it right?

yes this decoding is correct.

Best regards
igor
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Re: i.MX6 failed DRAM address decode

Kazuma_Sasaki — Thu, 01 Aug 2019 05:02:02 GMT

Hi Igor,

I appreciate your quickly support.

Best Regards,

Kazuma Sasaki.