i.MX Processors中的主题 Re: iMX6UL: Power-down counter Event

iMX6UL: Power-down counter Event

prabhatkumar — Wed, 17 Jul 2019 19:09:29 GMT

How do we test iMX6UL power down counter event in Sec 58.5.3?

In uboot, we don't touch WDOG1_WMCR PDE bit. It stays 1 and expect CPU to reboot after 16 seconds but CPU does not boot.

Am I missing any configuration?

Re: iMX6UL: Power-down counter Event

karangajjar — Thu, 18 Jul 2019 05:22:42 GMT

Hi Prabhat Kumar,

Can you please let us know the steps you are executing and expecting the CPU to reset in 16 seconds?

Regards,

Karan Gajjar

Re: iMX6UL: Power-down counter Event

igorpadykov — Thu, 18 Jul 2019 05:29:49 GMT

Hi Prabhat

after reset "Power-down counter Event" signal is not routed externally, for

example LCD_RESET (used as "nWDOG" on i.MX6UL EVK) is configured as

gpio input, described in Table 94. 9x9 mm Functional Contact Assignments

i.MX 6UltraLite Applications Processors for Consumer Products Data Sheet

MCIMX6UL-EVK_DESIGNFILES

Design files, including hardware schematics, Gerbers, and OrCAD files.

Best regards
igor
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Re: iMX6UL: Power-down counter Event

prabhatkumar — Thu, 18 Jul 2019 15:44:27 GMT

Hi Karan,

According to Reference Manual, if PDE bit in WMCR register is not disabled CPU should reset. I corrupted uboot so that uboot does not work. So, I expect CPU to reset and load uboot normally but CPU does not reset after 16 seconds.

Re: iMX6UL: Power-down counter Event

prabhatkumar — Thu, 18 Jul 2019 15:55:20 GMT

Hi Igor,

Thank for the quick reply.

The way I understood is when CPU boots its loads u-boot and PDE bit in WCMR register gets disabled. This means u-boot load was success then mux WDOG_ANY in u-boot and boot into Linux.

Is that correct?

If u-boot fails to load then PDE bit is still high (1) and should cause reset in 16 seconds. I don't see this behavior. CPU does not reset. What could be wrong here? LCD_RESET (WDOG_ANY) does not come into play yet.

PS: I am using QSPI not serial down loader

Re: iMX6UL: Power-down counter Event

igorpadykov — Fri, 19 Jul 2019 04:33:23 GMT

Hi Prabhat

I do not think that uboot uses such algorithms.

Best regards
igor

Re: iMX6UL: Power-down counter Event

prabhatkumar — Fri, 19 Jul 2019 16:05:59 GMT

Hi Igor,

Then, in what case PDE bit in WCMR register cause CPU reset? I queried PDE bit in uboot and see that its been disabled.

Lets say If uboot is corrupted, will PDE bit will cause reset? It was my understanding that u-boot disables PDE bit.

Re: iMX6UL: Power-down counter Event

igorpadykov — Fri, 19 Jul 2019 23:25:22 GMT

Hi Prabhat

uboot does not use that functionality, one can add any additional features by himself.

For resetting WDOG_ANY should be configured properly (using iomux), add codes for example

to dcd header

imximage.cfg\mx6ul_14x14_evk\freescale\board - uboot-imx - i.MX U-Boot

and also it should shortly power off all board, as it is done in i.MX6UL EVK schematic: nWDOG, U708

p.10 SPF-28617

Design files, including hardware schematics, Gerbers, and OrCAD files

Best regards
igor