<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: i.MX8M Mini L2 cache access</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-L2-cache-access/m-p/934485#M140033</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi m.c.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;seems not as discussed on arm forum:&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/5303/using-the-whole-cortex-a-l2-cache-without-external-memory" title="https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/5303/using-the-whole-cortex-a-l2-cache-without-external-memory"&gt;Using the whole Cortex-A L2 Cache without external memory - Cortex-A / A-Profile forum - Processors - Arm Community&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;DDR memory would be fastest access as it is designed for such purpose.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 02 Oct 2019 10:50:59 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2019-10-02T10:50:59Z</dc:date>
    <item>
      <title>i.MX8M Mini L2 cache access</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-L2-cache-access/m-p/934484#M140032</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Is it possible to acess L2 cache in bare metal mode (jailhouse inmate)? If not, which memory has fastest access time that bare matel mode can access?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Oct 2019 09:17:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-L2-cache-access/m-p/934484#M140032</guid>
      <dc:creator>m_c</dc:creator>
      <dc:date>2019-10-02T09:17:47Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8M Mini L2 cache access</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-L2-cache-access/m-p/934485#M140033</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi m.c.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;seems not as discussed on arm forum:&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/5303/using-the-whole-cortex-a-l2-cache-without-external-memory" title="https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/5303/using-the-whole-cortex-a-l2-cache-without-external-memory"&gt;Using the whole Cortex-A L2 Cache without external memory - Cortex-A / A-Profile forum - Processors - Arm Community&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;DDR memory would be fastest access as it is designed for such purpose.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Oct 2019 10:50:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-L2-cache-access/m-p/934485#M140033</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-10-02T10:50:59Z</dc:date>
    </item>
  </channel>
</rss>

