<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: IPU QoS Priority</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IPU-QoS-Priority/m-p/931518#M139721</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Kazuma Sasaki,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The AXI IDs refer to different channels on the IPU so you can set the priority of each channel accordingly. You can see a bit more on this on the “Handling real time channels” section of the Reference Manual.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regarding your second question you are correct, a higher binary value translates to a higher priority. &amp;nbsp;1000b is the lowest priority and 1111b is the highest priority. If you wish to force a specific priority trough these registers you need to use 1 on the MSB, otherwise the priority will be passed as configured.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope this information helps!&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 17 Jul 2019 19:57:02 GMT</pubDate>
    <dc:creator>gusarambula</dc:creator>
    <dc:date>2019-07-17T19:57:02Z</dc:date>
    <item>
      <title>IPU QoS Priority</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IPU-QoS-Priority/m-p/931517#M139720</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;RM Rev. 4, 07/2018 mentioned we can set the priority for IPU module as below.&lt;/P&gt;&lt;P&gt;However, I could not find any description in RM. Could you please teach us following points?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Q1. What does meaning of AXI ID 11, 10, 01 and 00?&lt;/P&gt;&lt;P&gt;Q2. What does meaning of bit field? 0000b is the lowest priority and 0111b is the highest priority. Is it right?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/81748iF3C09A5EBDC4F061/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Kazuma Sasaki.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 17 Jul 2019 10:27:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IPU-QoS-Priority/m-p/931517#M139720</guid>
      <dc:creator>Kazuma_Sasaki</dc:creator>
      <dc:date>2019-07-17T10:27:41Z</dc:date>
    </item>
    <item>
      <title>Re: IPU QoS Priority</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IPU-QoS-Priority/m-p/931518#M139721</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Kazuma Sasaki,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The AXI IDs refer to different channels on the IPU so you can set the priority of each channel accordingly. You can see a bit more on this on the “Handling real time channels” section of the Reference Manual.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regarding your second question you are correct, a higher binary value translates to a higher priority. &amp;nbsp;1000b is the lowest priority and 1111b is the highest priority. If you wish to force a specific priority trough these registers you need to use 1 on the MSB, otherwise the priority will be passed as configured.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope this information helps!&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 17 Jul 2019 19:57:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IPU-QoS-Priority/m-p/931518#M139721</guid>
      <dc:creator>gusarambula</dc:creator>
      <dc:date>2019-07-17T19:57:02Z</dc:date>
    </item>
    <item>
      <title>Re: IPU QoS Priority</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IPU-QoS-Priority/m-p/931519#M139722</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/gusarambula"&gt;gusarambula&lt;/A&gt;‌,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I appreciate your support. it is very useful information for us.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Let me confirm one more thing.&lt;/P&gt;&lt;P&gt;From section of the 38.4.2.4.1 Handling real time channels in the Reference Manual.&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;In order to do that, the user has to set the channel's ID according to the settings in the&lt;BR /&gt;memory controller and set the priority of the channel according to its nature. The buffer&lt;BR /&gt;controller (BCW/BCR) holds all the pending requests that won the arbitration. However,&lt;BR /&gt;as&lt;STRONG&gt; the memory controller can distinguish between the real time channels and non real&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;time channels within the IPU&lt;/STRONG&gt;, there could be a situation where the real time requests are&lt;BR /&gt;blocked as the IPU's queue is filled with non real time requests. To avoid that, &lt;STRONG&gt;the user&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;can limit the number of non-real time requests in the queue.&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;The queue for read requests can handle up to 8 requests. The queue for write requests can&lt;BR /&gt;handle up to 6 requests. The user can limit the number of non real time requests by&lt;BR /&gt;setting the USED_BUFS_MAX_W for write requests and USED_BUFS_MAX_R for&lt;BR /&gt;read requests. The feature that limits the number of requests is enabled by setting the&lt;BR /&gt;USED_BUFS_EN_R bit for the read requests and USED_BUFS_EN_W for the write&lt;BR /&gt;requests.&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We would like to limit the number of non-real time stream to avoid IPU bus filling error.&lt;/P&gt;&lt;P&gt;How do we chose real time channels of IDMAC?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Kazuma Sasaki.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 18 Jul 2019 04:01:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IPU-QoS-Priority/m-p/931519#M139722</guid>
      <dc:creator>Kazuma_Sasaki</dc:creator>
      <dc:date>2019-07-18T04:01:31Z</dc:date>
    </item>
  </channel>
</rss>

