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    <title>topic Re: iMX6 Quad PoP Package supporting LPDDR2  in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Quad-PoP-Package-supporting-LPDDR2/m-p/930970#M139628</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Sir,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your kind reply. We are planning to use&amp;nbsp;&lt;SPAN style="font-size: 11.0pt;"&gt;MCIMX6Q7CZK08AE in our system to get smallest form factor. Moreover&amp;nbsp;MT42L128M64D2LL-25 is obsolete. So &lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;EDB8164B4PT-1DAT-F&lt;SPAN&gt;&amp;nbsp;is&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;replacement of the same. But still clock enable is crossed.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;Please clarify.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;Thanks&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 17 Jun 2019 08:38:02 GMT</pubDate>
    <dc:creator>pranavparmar</dc:creator>
    <dc:date>2019-06-17T08:38:02Z</dc:date>
    <item>
      <title>iMX6 Quad PoP Package supporting LPDDR2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Quad-PoP-Package-supporting-LPDDR2/m-p/930968#M139626</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Reader,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I want to use the PoP version of iMX6 in my new design. But there are no reference schematics for the same. Neither are any supported LPDDR2 memories described. I reference some of the blogs regarding the same in community and found that&amp;nbsp;&lt;SPAN style="font-size: 11.0pt;"&gt;EDB8164B4PT-1DAT-F is compatible.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;When I saw the pin connection between two I made following observation:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;As per the ball assignment processor &lt;STRONG&gt;channel 1&lt;/STRONG&gt; is connected to memory &lt;STRONG&gt;die 0&lt;/STRONG&gt; and, processor &lt;STRONG&gt;channel 0&lt;/STRONG&gt; is connected to memory &lt;STRONG&gt;die 1&lt;/STRONG&gt;. But he Clock Enable signal (CKE_Px) is exchanged, i.e. Processor &lt;STRONG&gt;CKE0_P0&lt;/STRONG&gt; is connected to Memory &lt;STRONG&gt;CKE_A&lt;/STRONG&gt; and &lt;STRONG&gt;CKE0_P1 &lt;/STRONG&gt;is connected to &lt;STRONG&gt;CKE_B&lt;/STRONG&gt;.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Will this configuration work? Or is there any other LPDDR supported?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance.&lt;/P&gt;&lt;P&gt;Pranav&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 17 Jun 2019 05:08:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-Quad-PoP-Package-supporting-LPDDR2/m-p/930968#M139626</guid>
      <dc:creator>pranavparmar</dc:creator>
      <dc:date>2019-06-17T05:08:07Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6 Quad PoP Package supporting LPDDR2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Quad-PoP-Package-supporting-LPDDR2/m-p/930969#M139627</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Pranav&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;one can look at below links (also some info were sent via mail)&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/472137"&gt;https://community.nxp.com/thread/472137&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://source.codeaurora.org/external/imx/linux-imx/tree/?h=scm-imx_4.1.15_2.0.0_ga" title="https://source.codeaurora.org/external/imx/linux-imx/tree/?h=scm-imx_4.1.15_2.0.0_ga"&gt;linux-imx - i.MX Linux kernel&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 17 Jun 2019 06:38:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-Quad-PoP-Package-supporting-LPDDR2/m-p/930969#M139627</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-06-17T06:38:30Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6 Quad PoP Package supporting LPDDR2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Quad-PoP-Package-supporting-LPDDR2/m-p/930970#M139628</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Sir,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your kind reply. We are planning to use&amp;nbsp;&lt;SPAN style="font-size: 11.0pt;"&gt;MCIMX6Q7CZK08AE in our system to get smallest form factor. Moreover&amp;nbsp;MT42L128M64D2LL-25 is obsolete. So &lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;EDB8164B4PT-1DAT-F&lt;SPAN&gt;&amp;nbsp;is&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;replacement of the same. But still clock enable is crossed.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;Please clarify.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;Thanks&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 17 Jun 2019 08:38:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-Quad-PoP-Package-supporting-LPDDR2/m-p/930970#M139628</guid>
      <dc:creator>pranavparmar</dc:creator>
      <dc:date>2019-06-17T08:38:02Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6 Quad PoP Package supporting LPDDR2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-Quad-PoP-Package-supporting-LPDDR2/m-p/930971#M139629</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;DRAM_CKE0P0&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; AA29 , DRAM_CKE1P0&amp;nbsp;&amp;nbsp; Y29 in Table 85. 12 x 12 mm&lt;/P&gt;&lt;P&gt;&amp;nbsp;Functional Contact Assignments i.MX 6Dual/6Quad Consumer-PoP&lt;/P&gt;&lt;P&gt;Applications Processor Data Sheet are defined per sect.2.1 LPDDR2 12x12 PoP 2-channel 2x32 package&lt;/P&gt;&lt;P&gt;ballout LPDDR2 JESD209-2D specification.&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/data-sheet/IMX6DQCPOPEC.pdf" title="https://www.nxp.com/docs/en/data-sheet/IMX6DQCPOPEC.pdf"&gt;https://www.nxp.com/docs/en/data-sheet/IMX6DQCPOPEC.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/87275i66D1B7EF7836A7D2/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.jpg" alt="pastedImage_1.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 17 Jun 2019 11:47:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-Quad-PoP-Package-supporting-LPDDR2/m-p/930971#M139629</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-06-17T11:47:44Z</dc:date>
    </item>
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