i.MX ProcessorsのトピックRe: MCIMX8M-EVKB design

MCIMX8M-EVKB design

nadira — Mon, 16 Sep 2019 10:02:51 GMT

3.3V J1001 HDMI CEC signal is connected HDMI_CEC with no level shift to 1.8V as HDMI_AVDDIO is 1.8V. Also HPD signal as highlighted in below schematics

The D1003 voltage drop is 0.59V only.

Re: MCIMX8M-EVKB design

Rita_Wang — Mon, 23 Sep 2019 03:07:56 GMT

Hi，

Do you mean the HDMI_CEC power? Could you tell us your question exactly. I will confirm it for you.

Have a nice day

Rita

Re: MCIMX8M-EVKB design

nadira — Mon, 23 Sep 2019 04:28:15 GMT

Hi Rita,

As per design HDMI_CEC is connected to IMX8 Processor. The Signal HDMI_CEC in generally 3.3V logic signal, but my question here is As per design HDMI_AVDDIO is 1.8V this means interface is tolerant to 1.8V logic signals only. So why this HDMI_CEC (3.3V logic Signal) Connected to IMX8 Processor without any level translator?

Regards,

Yaseen

Re: MCIMX8M-EVKB design

Rita_Wang — Tue, 24 Sep 2019 05:58:32 GMT

Hi Yaseen,

I am confirming it for you. And will give you reply as soon as possible.

Have a nice day

Rita

Re: MCIMX8M-EVKB design

nadira — Tue, 01 Oct 2019 12:37:43 GMT

Hi Rita Wang,

How are you?

Any updates for my question.

Regards,

Yaseen

Re: MCIMX8M-EVKB design

Rita_Wang — Wed, 13 Jan 2021 00:15:33 GMT

Hi Yaseen,

Sorry for late reply, I am not at work on last days. About your above questions, I have confirmed with our expert team. Here is the reply:

There are some mistakes in the 8m datasheet;

power domain of HDMI_CEC, HDMI_DDC_SCL, HDMI_DDC_SDA are not correct;

HDMI_CEC, HDMI_DDC_SCL, HDMI_DDC_SDA are connected directly the HDMI PHY;

HDMI_CEC is 3.3V;

HDMI_DDC_SCL, HDMI_DDC_SDA are up to 5v;

image-2019-10-08-20-15-05-914.png

Have a nice day

Rita