topic Re: I.MX8M Mini LPDDR4 issue at EVK Schematic. in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/I-MX8M-Mini-LPDDR4-issue-at-EVK-Schematic/m-p/929357#M139459 <HTML><HEAD></HEAD><BODY><P>We have confirmed it for you that:</P><P><SPAN style="background: white; color: #414142;">There are 2 channels in LPDDR4</SPAN><SPAN style="background: white; color: #414142;">，</SPAN><SPAN style="background: white; color: #414142;">the design in 8MM change the all signals between channel A and B for easier routing. It can be support.</SPAN></P></BODY></HTML> Tue, 24 Sep 2019 08:35:37 GMT Rita_Wang 2019-09-24T08:35:37Z I.MX8M Mini LPDDR4 issue at EVK Schematic. https://community.nxp.com/t5/i-MX-Processors/I-MX8M-Mini-LPDDR4-issue-at-EVK-Schematic/m-p/929356#M139458 <HTML><HEAD></HEAD><BODY><P>#i.MX8M Mini&nbsp;</P><P></P><P>Dear&nbsp;</P><P>I want to design with I.MX8M Mini&nbsp; also I will utilize EVK B/D for connection LPDDR4.</P><P>today, I found some curious point at LPDDR4 part at EVK schematic.</P><P>upper picture captured from Mini. and below picture captured 8M evk also.</P><P>Can you guide me, I want to design LPDDR4 with&nbsp;<SPAN style="color: #414142; background-color: #ffffff;">MT53D1024M32D4DT-053 WT:D (4GB) base on i.MX8M Mini.</SPAN></P><P><SPAN style="color: #414142; background-color: #ffffff;">Even though, EVK design with 2GB, NC chipselect pin remain DRAM nCS1B, DRAM nCS1A, so I could design with 4GB.(<SPAN>MT53D1024M32D4DT-053 WT:D ).</SPAN></SPAN></P><P><SPAN style="color: #414142; background-color: #ffffff;"><SPAN>But, why A side B side was different when comparing 8M. DDR connection picture.?</SPAN></SPAN></P><P><SPAN style="color: #414142; background-color: #ffffff;"><SPAN>Can you support me about this points ASAP?</SPAN></SPAN></P><P><SPAN style="color: #414142; background-color: #ffffff;"><SPAN>&nbsp;</SPAN></SPAN></P><P><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/84987iD384D4684EF038EB/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /></span></P><P><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/85033i00FC719F907845D8/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /></span></P></BODY></HTML> Mon, 16 Sep 2019 14:46:07 GMT https://community.nxp.com/t5/i-MX-Processors/I-MX8M-Mini-LPDDR4-issue-at-EVK-Schematic/m-p/929356#M139458 netchip 2019-09-16T14:46:07Z Re: I.MX8M Mini LPDDR4 issue at EVK Schematic. https://community.nxp.com/t5/i-MX-Processors/I-MX8M-Mini-LPDDR4-issue-at-EVK-Schematic/m-p/929357#M139459 <HTML><HEAD></HEAD><BODY><P>We have confirmed it for you that:</P><P><SPAN style="background: white; color: #414142;">There are 2 channels in LPDDR4</SPAN><SPAN style="background: white; color: #414142;">，</SPAN><SPAN style="background: white; color: #414142;">the design in 8MM change the all signals between channel A and B for easier routing. It can be support.</SPAN></P></BODY></HTML> Tue, 24 Sep 2019 08:35:37 GMT https://community.nxp.com/t5/i-MX-Processors/I-MX8M-Mini-LPDDR4-issue-at-EVK-Schematic/m-p/929357#M139459 Rita_Wang 2019-09-24T08:35:37Z Re: I.MX8M Mini LPDDR4 issue at EVK Schematic. https://community.nxp.com/t5/i-MX-Processors/I-MX8M-Mini-LPDDR4-issue-at-EVK-Schematic/m-p/929358#M139460 <HTML><HEAD></HEAD><BODY><P>This is the block diagram of&nbsp;2GB LPDDR4.</P><P><IMG src="https://community.nxp.com/servlet/JiveServlet/download/1210180-1-456180/LPDDR4.png" style="max-width: 100%; max-height: 100%;" /></P></BODY></HTML> Tue, 24 Sep 2019 08:57:17 GMT https://community.nxp.com/t5/i-MX-Processors/I-MX8M-Mini-LPDDR4-issue-at-EVK-Schematic/m-p/929358#M139460 Rita_Wang 2019-09-24T08:57:17Z