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    <title>i.MX Processors中的主题 Re: i.MX8M Mini DDR Package trace length/delay</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-DDR-Package-trace-length-delay/m-p/922386#M138659</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Most are aware of the DDRx timing constraints and PCB+package bondwire implications. Those lengths are in Table 27 of teh design guide. What about for other high speed signals?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I intend to use the FlexSPI in Octal mode to an FPGA. The DDR transfer mode is at 166MHz (max). The timing looks quite tight.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can NXP provide package bond wire length for all pins? DDR, FlexSPI, and beyond? Xilinx provides this for all pins, all current devices.&lt;/P&gt;&lt;P&gt;In particular, I am using the&amp;nbsp;MIMX8MM3CVTKZAA.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Stay safe,&lt;/P&gt;&lt;P&gt;Dennis&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sun, 05 Apr 2020 23:20:33 GMT</pubDate>
    <dc:creator>dennisespey</dc:creator>
    <dc:date>2020-04-05T23:20:33Z</dc:date>
    <item>
      <title>i.MX8M Mini DDR Package trace length/delay</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-DDR-Package-trace-length-delay/m-p/922384#M138657</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We designing &lt;SPAN&gt;i.MX8M Mini custom&lt;/SPAN&gt;&amp;nbsp;board&amp;nbsp;using LPDDR4 memory. For&amp;nbsp;LPDDR4 length match,&amp;nbsp; we need to consider&amp;nbsp;i.MX 8M Mini DDR package trace delays(ps)-which is given in picosec as&amp;nbsp;per Table 27 in&amp;nbsp; i.MX 8M Mini Hardware Developer’s Guide.&amp;nbsp;&lt;/P&gt;&lt;P&gt;We need to get information on IMx8MMini&amp;nbsp;DDR Package&amp;nbsp; trace length in microns/mils for DDR length match in our board.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;How can i convert&amp;nbsp;&amp;nbsp;&lt;SPAN&gt;IMx8MMini&amp;nbsp;&lt;/SPAN&gt;DDR Package Trace delay from ps to trace length in mils/micron. Please&amp;nbsp;help and support us.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Shruthi&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 May 2019 09:50:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-DDR-Package-trace-length-delay/m-p/922384#M138657</guid>
      <dc:creator>shruthi_subrama</dc:creator>
      <dc:date>2019-05-29T09:50:34Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8M Mini DDR Package trace length/delay</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-DDR-Package-trace-length-delay/m-p/922385#M138658</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The actual in-package wire length data is not useful in your case since the signal fly time on in-package wire may differ from the on-board trace signal fly time.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;You can calculate the virtual trace length deltas for each DDR interface signal based on known on-board trace signal fly time per unit of length and the in-package signal propagation delay times, given in the Table 27.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 31 May 2019 11:57:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-DDR-Package-trace-length-delay/m-p/922385#M138658</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2019-05-31T11:57:02Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8M Mini DDR Package trace length/delay</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-DDR-Package-trace-length-delay/m-p/922386#M138659</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Most are aware of the DDRx timing constraints and PCB+package bondwire implications. Those lengths are in Table 27 of teh design guide. What about for other high speed signals?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I intend to use the FlexSPI in Octal mode to an FPGA. The DDR transfer mode is at 166MHz (max). The timing looks quite tight.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can NXP provide package bond wire length for all pins? DDR, FlexSPI, and beyond? Xilinx provides this for all pins, all current devices.&lt;/P&gt;&lt;P&gt;In particular, I am using the&amp;nbsp;MIMX8MM3CVTKZAA.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Stay safe,&lt;/P&gt;&lt;P&gt;Dennis&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 05 Apr 2020 23:20:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Mini-DDR-Package-trace-length-delay/m-p/922386#M138659</guid>
      <dc:creator>dennisespey</dc:creator>
      <dc:date>2020-04-05T23:20:33Z</dc:date>
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