i.MX6ULL SPI question

m_c — Wed, 14 Aug 2019 10:07:35 GMT

In i.Mx6ULL reference manual.

1. For single burst. Is it mean transfer single FIFO and waiting for software to write data to FIFO? SS is an don't care pin, until FIFO transfer complete?

2. For multi burst. Is it mean transfer different FIFO, SS pin will assert if any FIFO transfer complete? Then transfer another FIFO? The burst won't finish until all FIFO transfer complete?

Re: i.MX6ULL SPI question

Yuri — Thu, 15 Aug 2019 09:10:18 GMT

Hello,

For the first case the maximum length of the single SPI burst is defined by FIFO. When FIFO is

underflowed (empty) the SS is negated. ECSPIx_PERIODREG may be used to setup delays between

SPI transfers.

For the second - multiple words, as defined in the BURST LENGTH field of the ECSPI_CONREG register,

will be transferred with SS negation.

Have a great day,

Yuri

-------------------------------------------------------------------------------

Note:

- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored

Please open a new thread and refer to the closed one, if you have a related question at a later point in time.

i.MX Processorsのトピックi.MX6ULL SPI question

i.MX6ULL SPI question

Re: i.MX6ULL SPI question