topic PCIE layout routing recommendations ? in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/PCIE-layout-routing-recommendations/m-p/914028#M137608 <HTML><HEAD></HEAD><BODY><P>Dear All,</P><P></P><P>For the PCIE differential pairs we need to use differential pairs for routing.&nbsp;</P><P></P><P>Is that okay to route as single ended signal for pull down resistors(49.9 Ohms) or pull ups ? Will it affect for PCIE differential pairs if we route pull down as single ended signal ? What should be the impedance for those traces?</P><P></P><P></P><P><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/83991iEBA53F6D5AC4F7B5/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /></span></P><P></P><P></P><P><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/83993i130F5836BC0645BD/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /></span></P><P></P><P>Regards,</P><P>Peter.</P></BODY></HTML> Tue, 28 May 2019 09:39:53 GMT peteramond 2019-05-28T09:39:53Z PCIE layout routing recommendations ? https://community.nxp.com/t5/i-MX-Processors/PCIE-layout-routing-recommendations/m-p/914028#M137608 <HTML><HEAD></HEAD><BODY><P>Dear All,</P><P></P><P>For the PCIE differential pairs we need to use differential pairs for routing.&nbsp;</P><P></P><P>Is that okay to route as single ended signal for pull down resistors(49.9 Ohms) or pull ups ? Will it affect for PCIE differential pairs if we route pull down as single ended signal ? What should be the impedance for those traces?</P><P></P><P></P><P><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/83991iEBA53F6D5AC4F7B5/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /></span></P><P></P><P></P><P><span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"><img src="https://community.nxp.com/t5/image/serverpage/image-id/83993i130F5836BC0645BD/image-size/large?v=v2&amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /></span></P><P></P><P>Regards,</P><P>Peter.</P></BODY></HTML> Tue, 28 May 2019 09:39:53 GMT https://community.nxp.com/t5/i-MX-Processors/PCIE-layout-routing-recommendations/m-p/914028#M137608 peteramond 2019-05-28T09:39:53Z Re: PCIE layout routing recommendations ? https://community.nxp.com/t5/i-MX-Processors/PCIE-layout-routing-recommendations/m-p/914029#M137609 <HTML><HEAD></HEAD><BODY><P><SPAN style="font-size: 10.0pt; color: black;">Generally, the differential Clock and the differential pairs of data transceiver and receiver&nbsp; are <SPAN class=""></SPAN>Full Equal Length, and make the line as short as possible. And the impedance is 100Ohm for clock differential, and 85 for Data difference pair.</SPAN></P><TABLE border="0" cellpadding="0" cellspacing="0" style="width: 14px;"><TBODY><TR><TD style="width: 10px;"></TD><TD style="width: 10px;"></TD></TR></TBODY></TABLE></BODY></HTML> Wed, 05 Jun 2019 07:11:48 GMT https://community.nxp.com/t5/i-MX-Processors/PCIE-layout-routing-recommendations/m-p/914029#M137609 Rita_Wang 2019-06-05T07:11:48Z