<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: USB3 superspeed errors, PTN36043 configuration</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/USB3-superspeed-errors-PTN36043-configuration/m-p/913935#M137599</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There are no reports of communication errors using the PTN36043A super speed interface.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;When PTN36043A is not being powered (i.e., VDD1V8 = 0 V), special steps should be done to prevent back-current issues on control pins such SEL or CH1/2_SET1/2 pins when these pins' states are not low. These pins can be controlled through two different ways. – pull-up/pull-down resistors - make sure these pull-up resistors' VDD is the same power source as to power PTN36043A. When power to PTN36043A is off, power to these pull-up resistors will be off as well. – external processor's GPIO - if PTN36043A is turned off when the external processor's power stays on, processor should configure these GPIOs connected to these control pins as output low (&amp;lt; 0.4 V) or tri-state mode (configure GPIOs as input mode). This will make sure no current will be flowing into PTN36043A through these control pins.&lt;/P&gt;&lt;P&gt;The recommended value of the external pull-up/pull-down resistor is 30 kohms.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Make sure you have configured the CHx_SETx according to your high-speed signal path:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/88043i8C63F4AF613D1BFB/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/88044i1648F20A53D9383E/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Jose&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 17 Jun 2019 17:28:08 GMT</pubDate>
    <dc:creator>reyes</dc:creator>
    <dc:date>2019-06-17T17:28:08Z</dc:date>
    <item>
      <title>USB3 superspeed errors, PTN36043 configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/USB3-superspeed-errors-PTN36043-configuration/m-p/913934#M137598</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We are currently deeply inspecting the i.MX8M USB3 superspeed interface, on our custom design and also on the i.MX8M EVK. With some combinations of cables and notebook, we experience communication errors.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Currently we suspect that the PTN36043 mux/redriver is not configured correctly, regarding the de-emphasis/equalization/tx level settings using the CHx_SETx pins. The i.MX8M EVK has the corresponding CHx_SETx pins tied to high by default, another answer in this forum implies that an "all open" setting would be the best starting point. BTW: the i.MX8M EVK and our custom design have rather short USB traces.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So: is there any experience from NXP or other designers regarding the CHx_SETx pin settings?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;regards,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thomas.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 12 Jun 2019 09:44:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/USB3-superspeed-errors-PTN36043-configuration/m-p/913934#M137598</guid>
      <dc:creator>thomasdoerfler</dc:creator>
      <dc:date>2019-06-12T09:44:56Z</dc:date>
    </item>
    <item>
      <title>Re: USB3 superspeed errors, PTN36043 configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/USB3-superspeed-errors-PTN36043-configuration/m-p/913935#M137599</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There are no reports of communication errors using the PTN36043A super speed interface.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;When PTN36043A is not being powered (i.e., VDD1V8 = 0 V), special steps should be done to prevent back-current issues on control pins such SEL or CH1/2_SET1/2 pins when these pins' states are not low. These pins can be controlled through two different ways. – pull-up/pull-down resistors - make sure these pull-up resistors' VDD is the same power source as to power PTN36043A. When power to PTN36043A is off, power to these pull-up resistors will be off as well. – external processor's GPIO - if PTN36043A is turned off when the external processor's power stays on, processor should configure these GPIOs connected to these control pins as output low (&amp;lt; 0.4 V) or tri-state mode (configure GPIOs as input mode). This will make sure no current will be flowing into PTN36043A through these control pins.&lt;/P&gt;&lt;P&gt;The recommended value of the external pull-up/pull-down resistor is 30 kohms.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Make sure you have configured the CHx_SETx according to your high-speed signal path:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/88043i8C63F4AF613D1BFB/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/88044i1648F20A53D9383E/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Jose&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 17 Jun 2019 17:28:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/USB3-superspeed-errors-PTN36043-configuration/m-p/913935#M137599</guid>
      <dc:creator>reyes</dc:creator>
      <dc:date>2019-06-17T17:28:08Z</dc:date>
    </item>
  </channel>
</rss>

