<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: About Power mode transitions in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912245#M137444</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;internal PMIC configuration is not supported in i.MX7D.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 12 Sep 2019 07:20:28 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2019-09-12T07:20:28Z</dc:date>
    <item>
      <title>About Power mode transitions</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912242#M137441</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;hello,Community&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For the circuit, see Figure 6-4. Chip reset scheme under PMU control in the i.MX 7 Dual Applications Processor Reference Manual.&lt;BR /&gt;Table 6-8. Assuming Configuration with internal PMIC column for Power mode transitions&lt;BR /&gt;When a high level signal is input from the OFF state to the ONOFF input, it starts up in the OFF to ON, by button state.&lt;BR /&gt;Then, will there be a transition to the automatic Emergency ON to OFF, by button state? (ONOFF input is level signal high continuous input)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="border: 0px currentColor; color: #51626f; background-color: #ffffff;"&gt;best regards&lt;/P&gt;&lt;P style="border: 0px currentColor; color: #51626f; background-color: #ffffff;"&gt;Goto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Sep 2019 07:20:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912242#M137441</guid>
      <dc:creator>goto11</dc:creator>
      <dc:date>2019-09-11T07:20:05Z</dc:date>
    </item>
    <item>
      <title>Re: About Power mode transitions</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912243#M137442</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Goto&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;will there be a transition to the automatic Emergency ON to OFF, by button state?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes, in particular Table 5-3. Power Mode Transition shows RUN to SNVS transition by&lt;/P&gt;&lt;P&gt;ONOFF long press,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Sep 2019 23:30:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912243#M137442</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-09-11T23:30:43Z</dc:date>
    </item>
    <item>
      <title>Re: About Power mode transitions</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912244#M137443</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;hello,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;When an ON-level signal is input to the ONOFF input from the OFF state, it starts from OFF to ON depending on the button state.&lt;BR /&gt;Does the transition to Emergency ON to OFF, by button if the ONOFF input is not turned off and continues to be turned on?&lt;/P&gt;&lt;P&gt;Does the transition to Normal ON to OFF, by button state occur even if the transition from automatic emergency on to off is disabled?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px currentcolor;"&gt;best regards&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px currentcolor;"&gt;Goto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Sep 2019 00:42:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912244#M137443</guid>
      <dc:creator>goto11</dc:creator>
      <dc:date>2019-09-12T00:42:15Z</dc:date>
    </item>
    <item>
      <title>Re: About Power mode transitions</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912245#M137444</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;internal PMIC configuration is not supported in i.MX7D.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Sep 2019 07:20:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912245#M137444</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-09-12T07:20:28Z</dc:date>
    </item>
    <item>
      <title>Re: About Power mode transitions</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912246#M137445</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;hello,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;As a major premise, state transition of Configuration with internal PMIC is performed as Table 6-8. Power mode transitions.&lt;BR /&gt;But does that mean that SW is always on?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px currentcolor;"&gt;best regards&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px currentcolor;"&gt;Goto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Sep 2019 08:30:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912246#M137445</guid>
      <dc:creator>goto11</dc:creator>
      <dc:date>2019-09-12T08:30:54Z</dc:date>
    </item>
    <item>
      <title>Re: About Power mode transitions</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912247#M137446</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV class=""&gt;&lt;P&gt;internal PMIC configuration is not supported in i.MX7D, so software also&lt;/P&gt;&lt;P&gt;does not support that option.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Sep 2019 10:13:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912247#M137446</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-09-12T10:13:44Z</dc:date>
    </item>
    <item>
      <title>Re: About Power mode transitions</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912248#M137447</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;hello,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The circuit is considered based on "Figure 6-4. Chip reset scheme under PMU control".&lt;BR /&gt;Table 6-8. Power mode transitions Configuration with internal PMIC is not supported. Is there any document that describes the relationship between Power mode, ONOFF SW and PMIC_ON_REQ signal?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px currentcolor;"&gt;best regards&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px currentcolor;"&gt;Goto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Sep 2019 11:59:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912248#M137447</guid>
      <dc:creator>goto11</dc:creator>
      <dc:date>2019-09-12T11:59:21Z</dc:date>
    </item>
    <item>
      <title>Re: About Power mode transitions</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912249#M137448</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;unfortunately additional documentation is not available, please&lt;/P&gt;&lt;P&gt;note Table 6-8 gives general description of reset, while i.MX7D uses&lt;/P&gt;&lt;P&gt;only configuration with external PMIC.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 12 Sep 2019 13:28:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912249#M137448</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-09-12T13:28:30Z</dc:date>
    </item>
    <item>
      <title>Re: About Power mode transitions</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912250#M137449</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;hello,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There are two questions about the attached document&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;①About internal PMIC configuration is not supported in i.MX7D&lt;BR /&gt;Is the content as follows?&lt;BR /&gt;The configurations enclosed in red in Table 6-8 and Figure 6-4 are not supported.&lt;BR /&gt;Does it only support the configuration enclosed in blue in Table 6-8 and Figure 6-5?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;②About the attached document sch-28590_i.mx7d_saber_rev_d&lt;BR /&gt;The following signals are connected.&lt;BR /&gt;Is this connection an internal PMIC configuration?&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;Power Botton and i.MX7D ONOFF signal&lt;BR /&gt;&amp;nbsp; &amp;nbsp;i.MX7D PMIC_ON_REQ signal and PMIC PWRON signal&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px currentcolor;"&gt;best regards&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px currentcolor;"&gt;Goto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 19 Sep 2019 09:07:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912250#M137449</guid>
      <dc:creator>goto11</dc:creator>
      <dc:date>2019-09-19T09:07:07Z</dc:date>
    </item>
    <item>
      <title>Re: About Power mode transitions</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912251#M137450</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;for new questions suggest to create new thread.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 19 Sep 2019 09:34:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/About-Power-mode-transitions/m-p/912251#M137450</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-09-19T09:34:43Z</dc:date>
    </item>
  </channel>
</rss>

