<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX Processors中的主题 Re: What is OCRAM?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/What-is-OCRAM/m-p/911057#M137307</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Hello,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; According to app note AN12077 (Using the i.MX RT FlexRAM) OCRAM is used during boot:&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;The minimum configuration of OCRAM is 64 KB.&amp;nbsp; This is required due to ROM code requires at least &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;64 KB of RAM for its execution (device dependent).&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/application-note/AN12077.pdf" title="https://www.nxp.com/docs/en/application-note/AN12077.pdf"&gt;https://www.nxp.com/docs/en/application-note/AN12077.pdf&lt;/A&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; Customers can use OCRAM (after boot) as needed, in particular - for buffers.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; App note AN12437 (i.MX RT Series Performance Optimization) states, that "OCRAM shows higher &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;performance than TCM when accessed by DMA, while lower performance when accessed by MCU core.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt; The reason is that OCRAM and DMA are in this same bus fabric, with less latency during the access." &lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/application-note/AN12437.pdf" title="https://www.nxp.com/docs/en/application-note/AN12437.pdf"&gt;https://www.nxp.com/docs/en/application-note/AN12437.pdf&lt;/A&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Have a great day,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Yuri.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;-------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Note:&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 15 Oct 2019 02:47:04 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2019-10-15T02:47:04Z</dc:date>
    <item>
      <title>What is OCRAM?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/What-is-OCRAM/m-p/911056#M137306</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm using iMXRT1020-EVK board. I have seen RAM configuration in manual it says that the RAM is shared by ITCM, DTCM and OCRAM. After reading application note I got that different region can be used for different usage like ITCM (.text and critical code), DTCM (.data). but not found exact usage of OCRAM. In few doc it is used as user buffer but not sure..&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If it is for user buffer then what is the difference between DTCM and OCRAM?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Default Linker is configured as&lt;/P&gt;&lt;P&gt;ITCM - 64KB,&lt;/P&gt;&lt;P&gt;DTCM - 64KB&lt;/P&gt;&lt;P&gt;OCRAM - 128 KB&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have compiled few of example code and observed that data is placed in ITCM and DTCM but OCRAM always remain Free.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can i change allocation of OCRAM to 0 during run time?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 14 Oct 2019 05:20:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/What-is-OCRAM/m-p/911056#M137306</guid>
      <dc:creator>jtro</dc:creator>
      <dc:date>2019-10-14T05:20:27Z</dc:date>
    </item>
    <item>
      <title>Re: What is OCRAM?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/What-is-OCRAM/m-p/911057#M137307</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Hello,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&amp;nbsp; According to app note AN12077 (Using the i.MX RT FlexRAM) OCRAM is used during boot:&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;The minimum configuration of OCRAM is 64 KB.&amp;nbsp; This is required due to ROM code requires at least &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;64 KB of RAM for its execution (device dependent).&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/application-note/AN12077.pdf" title="https://www.nxp.com/docs/en/application-note/AN12077.pdf"&gt;https://www.nxp.com/docs/en/application-note/AN12077.pdf&lt;/A&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; Customers can use OCRAM (after boot) as needed, in particular - for buffers.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; App note AN12437 (i.MX RT Series Performance Optimization) states, that "OCRAM shows higher &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;performance than TCM when accessed by DMA, while lower performance when accessed by MCU core.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt; The reason is that OCRAM and DMA are in this same bus fabric, with less latency during the access." &lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/application-note/AN12437.pdf" title="https://www.nxp.com/docs/en/application-note/AN12437.pdf"&gt;https://www.nxp.com/docs/en/application-note/AN12437.pdf&lt;/A&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Have a great day,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Yuri.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;-------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Note:&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 15 Oct 2019 02:47:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/What-is-OCRAM/m-p/911057#M137307</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2019-10-15T02:47:04Z</dc:date>
    </item>
    <item>
      <title>Re: What is OCRAM?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/What-is-OCRAM/m-p/911058#M137308</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Are you saying OCRAM is used by primary bootloader reside in MCU (96KB)?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If yes then Is it possible to reduce OCRAM size after boot process? &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 15 Oct 2019 04:38:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/What-is-OCRAM/m-p/911058#M137308</guid>
      <dc:creator>jtro</dc:creator>
      <dc:date>2019-10-15T04:38:18Z</dc:date>
    </item>
    <item>
      <title>Re: What is OCRAM?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/What-is-OCRAM/m-p/911059#M137309</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp; Yes, OCRAM is used by the primary bootloader, located in the boot ROM of the MCU.&lt;/P&gt;&lt;P class=""&gt;OCRAM size cannot be zero. Look at &lt;SPAN class=""&gt;Table 2 (Static FlexRAM configuration defined by fuses in RT1020)&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;for allowed configurations in the app note.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;A class="" data-content-finding="Community" href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fwww.nxp.com%2Fdocs%2Fen%2Fapplication-note%2FAN12077.pdf" rel="nofollow" target="_blank"&gt;https://www.nxp.com/docs/en/application-note/AN12077.pdf&lt;/A&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;~Yuri.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 15 Oct 2019 05:37:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/What-is-OCRAM/m-p/911059#M137309</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2019-10-15T05:37:40Z</dc:date>
    </item>
    <item>
      <title>Re: What is OCRAM?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/What-is-OCRAM/m-p/911060#M137310</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm asking about change RAM allocation in run time by using &lt;STRONG&gt;FLEXRAM_AllocateRam&lt;/STRONG&gt; function after primary bootloader jumps to user application.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 15 Oct 2019 05:56:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/What-is-OCRAM/m-p/911060#M137310</guid>
      <dc:creator>jtro</dc:creator>
      <dc:date>2019-10-15T05:56:27Z</dc:date>
    </item>
    <item>
      <title>Re: What is OCRAM?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/What-is-OCRAM/m-p/911061#M137311</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; You can try it, but even in section 2.1.1.2 (Runtime configuration) of the app note AN12077&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;we can find the following note: " Consider at least 64 K B for the OCRAM configuration because&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt; the ROM code requires this portion of RAM for execution (stack/static data)".&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 15 Oct 2019 06:33:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/What-is-OCRAM/m-p/911061#M137311</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2019-10-15T06:33:03Z</dc:date>
    </item>
  </channel>
</rss>

