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    <title>topic i.MX6 Boot Issue in Production Boards in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Boot-Issue-in-Production-Boards/m-p/910326#M137148</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We have designed SoM based on i.MX6 Quad processor (PN;&amp;nbsp;&lt;SPAN style="font-size: 11.0pt; color: black;"&gt;MCIMX6Q6AVT10AD) with 1GB DDR3 ( PN:&amp;nbsp;IS43TR16128B -125KBLI). The DDR3 is routed in T-topology, with 4x DDR3 devices. The board is in production.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: black;"&gt;Our issue is that 20% of the modules fails to boot during production test. We have to re-try DDR calibration to make these modules passed. I am just wondering , is it normal to do a DDR calibration for each production lot? ( even if I don't change any design or component etc)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: black;"&gt;Recently we build 1000 modules together. We did a DDR calibration for this batch. But still all module built on this batch doesn't boot well with this DDR calibration setting..&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are using u-boot version:&lt;/P&gt;&lt;P&gt;u-boot-fslc_v2013.04-r0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 26 Sep 2019 04:04:49 GMT</pubDate>
    <dc:creator>ratheeshchandra</dc:creator>
    <dc:date>2019-09-26T04:04:49Z</dc:date>
    <item>
      <title>i.MX6 Boot Issue in Production Boards</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Boot-Issue-in-Production-Boards/m-p/910326#M137148</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We have designed SoM based on i.MX6 Quad processor (PN;&amp;nbsp;&lt;SPAN style="font-size: 11.0pt; color: black;"&gt;MCIMX6Q6AVT10AD) with 1GB DDR3 ( PN:&amp;nbsp;IS43TR16128B -125KBLI). The DDR3 is routed in T-topology, with 4x DDR3 devices. The board is in production.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: black;"&gt;Our issue is that 20% of the modules fails to boot during production test. We have to re-try DDR calibration to make these modules passed. I am just wondering , is it normal to do a DDR calibration for each production lot? ( even if I don't change any design or component etc)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt; color: black;"&gt;Recently we build 1000 modules together. We did a DDR calibration for this batch. But still all module built on this batch doesn't boot well with this DDR calibration setting..&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are using u-boot version:&lt;/P&gt;&lt;P&gt;u-boot-fslc_v2013.04-r0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 26 Sep 2019 04:04:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Boot-Issue-in-Production-Boards/m-p/910326#M137148</guid>
      <dc:creator>ratheeshchandra</dc:creator>
      <dc:date>2019-09-26T04:04:49Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6 Boot Issue in Production Boards</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Boot-Issue-in-Production-Boards/m-p/910327#M137149</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Ratheesh&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;may be recommended to try nxp uboot from source.codeaurora.org/external/imx/uboot-imx repository&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://source.codeaurora.org/external/imx/uboot-imx/tree/?h=imx_v2018.03_4.14.78_1.0.0_ga" title="https://source.codeaurora.org/external/imx/uboot-imx/tree/?h=imx_v2018.03_4.14.78_1.0.0_ga"&gt;uboot-imx - i.MX U-Boot&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;with latest ddr test &lt;A href="https://community.nxp.com/docs/DOC-105652"&gt;i.MX6/7 DDR Stress Test Tool V3.00&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;When running a calibration test, one gets the minimum value for which the test works, &lt;BR /&gt;the maximum value for which the test works, and the center point. Average together &lt;BR /&gt;all the centerpoint value to come up with the ideal setting, and then just make sure &lt;BR /&gt;that value is a good margin away (~12) from any of the minimum and maximum &lt;BR /&gt;values observed under any conditions.&amp;nbsp; Take a random sample of 5 - 10 boards and &lt;BR /&gt;run the stress test a few times on each board (~5). One can run the test at extreme &lt;BR /&gt;temperatures as well. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 26 Sep 2019 10:18:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6-Boot-Issue-in-Production-Boards/m-p/910327#M137149</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-09-26T10:18:51Z</dc:date>
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