topic Re: IMX6Q: Multicore/Preempt PCIe access in i.MX Processors

IMX6Q: Multicore/Preempt PCIe access

etim — Fri, 19 Apr 2019 13:08:28 GMT

Howdy-

I have a FPGA connected to an IMX6Q via PCIe that provides some registers. My questions center around multi-core FPGA register access. Admittedly I have not dug into the docs - I was hoping to leverage someone else's knowledge.

Can two cores access 2 different registers of the FPGA simultaneously using mmap'd memory (Program IO)?
1. What guarantees exclusive access? I'm guessing it's the NIC-301...
Can a DMA operation to the registers occur simultaneously with a normal PIO without SW guaranteeing exclusivity?
(Probably the same question as (1)) What happens when a thread that is actively doing a register read (PIO) is preempted/interrupted by another thread/ISR that also issues a PIO register read?

Thanks!

Tim

Re: IMX6Q: Multicore/Preempt PCIe access

b36401 — Tue, 23 Apr 2019 04:03:35 GMT

Actually it is OK if different cores are using some external (outside of the core) unit like PCI.
Of course the software need to make sure that in one exact moment only one thread uses it.
However it does not matter on which core it run.
And in case of Linux it manages it fine on multicore processor like i.MX6Q.

Have a great day,
Victor

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Re: IMX6Q: Multicore/Preempt PCIe access

etim — Tue, 23 Apr 2019 12:25:29 GMT

Thanks for your reply!

So there is no HW arbitration between two threads accessing the FPGA (PCIe)?

If 2 threads mmap the region of FPGA registers, nothing in HW protects against a single u32 access/read (like the AXI)? It's a purely up to SW to arbitrate?

Thinking about PCIe like a memory, I don't believe I've seen protection around every time I read from RAM... unless there is a difference with-respect-to how the core/MMU views accesses between RAM and PCIe device.

Thanks!

Re: IMX6Q: Multicore/Preempt PCIe access

b36401 — Thu, 16 May 2019 09:24:11 GMT

Yuri answered the question in another thread:
https://community.nxp.com/thread/502868