topic Re: DDR Configuration Question in i.MX Processors

DDR Configuration Question

kcassar — Wed, 17 Apr 2019 13:42:08 GMT

Hi,

We have designed a custom board based around the IMX6Q Sabre. A lot of the design is very similar, however we have gone for two 1GB RAM chips.

We have used DDR3 channels 0 and 3. when we try to calibrate the RAM using the stress tester it sees we have 2x1GB but fails as it tries to calibrate channels 1 and 2. If we only calibrate channel 0 it passes with no problems.

Is using channels 0 and 3 a valid configuration for the DDR or would I have to use channel 0 and 1?

If it is valid, how do I force the stress tester to ignore channels 1 and 2 during calibration?

Kind regards,

Kyle.

Re: DDR Configuration Question

Yuri — Thu, 18 Apr 2019 04:17:29 GMT

Hello,

i.MX6 MMDC supports 16-bit, 32-bit and 64-bit data bus, assuming

DRAM_D0 - DRAM_D15 as 16-bit bus,

DRAM_D0 - DRAM_D31 as 32-bit bus,

DRAM_D0 - DRAM_D63 as 64-bit bus.

Have a great day,
Yuri

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Re: DDR Configuration Question

kcassar — Thu, 18 Apr 2019 08:32:32 GMT

Hi Yuri,

Thanks for getting back to me.

Can it support 32 bit but using DRAM_D0 - DRAM_D15 and DRAM_D48 - DRAM_D63 and not using the middle 2 lanes?

Cheers,

Kyle.

Re: DDR Configuration Question

Yuri — Thu, 18 Apr 2019 10:26:14 GMT

No, the MMDC does not support 32 bit, using DRAM_D0 - DRAM_D15 and DRAM_D48 - DRAM_D63.

~Yuri.