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    <title>i.MX Processors中的主题 Re: Initialization of iMX8M ECSPI2 TPM 2.0 device Infineon SLB9670 failed when running TPM self test</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Initialization-of-iMX8M-ECSPI2-TPM-2-0-device-Infineon-SLB9670/m-p/897617#M135542</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I want to take back my previous claim that there are no signals come out from the SCLK pin, after adjusting my oscilloscope bandwidth to full, I am now able to see the SPI clock signals sent to the TPM device.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Another thing I noticed is that, when data is transferred between the SPI master and the TPM slave device during the TPM driver initialization:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;SPI MOSI - is set to HIGH and data bits sent through this line are superimposed on the 3.3V signal&lt;/P&gt;&lt;P&gt;SPI MISO - is set to LOW and data bits sent through this line properly&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;When initialization process completed and the SPI interface is idle,&lt;/P&gt;&lt;P&gt;SPI MOSI - is idle HIGH&lt;/P&gt;&lt;P&gt;SPI MISO - is idle LOW&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The current issue is that the TPM driver is able to read from a TPM register (through MISO) and Not able to write to a TPM register (though MOSI). Therefore, it seems the problem is on the MOSI line, is it because the data is sent through a MOSI line which is always at logic level HIGH, and that is causing the TPM device to ignore the data sent?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 21 May 2019 09:29:43 GMT</pubDate>
    <dc:creator>yuklin_soo</dc:creator>
    <dc:date>2019-05-21T09:29:43Z</dc:date>
    <item>
      <title>Initialization of iMX8M ECSPI2 TPM 2.0 device Infineon SLB9670 failed when running TPM self test</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Initialization-of-iMX8M-ECSPI2-TPM-2-0-device-Infineon-SLB9670/m-p/897616#M135541</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am trying to enable a TPM 2.0 device (Infineon SLB9670XQ2.0) &amp;nbsp;which is connected to the ECSPI2 bus of an IMX8MQ processor, and when booting up the target board, I encountered an issue that the initialization of the TPM device failed with the below error messages:&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x1B, rev-id 16)&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;2.0 TPM (device-id 0x1B, rev-id 16)&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;tpm tpm0: A TPM error (256) occurred attempting to generate an interrupt&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;tpm tpm0: [Firmware Bug]: TPM interrupt not working, polling instead&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;tpm tpm0: A TPM error (256) occurred continue selftest&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;tpm tpm0: starting up the TPM manually&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;tpm tpm0: tpm_transmit: tpm_recv: error -5&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;tpm tpm0: TPM self test failed&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;tpm_tis_spi: probe of spi1.0 failed with error -5&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;The TPM self test failed because the TPM device is not able to generate an interrupt. Display of kernel debugging messages shows that, prior to the TPM self test, the TPM driver failed to set the Global Interrupt Enable bit on the TPM Interrupt Enable register to 1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;To find out why the driver can’t write to a TPM register, we tried to monitor the SPI Slave Select GPIO pin on oscilloscope during the SPI data transfer (interrupt-driven PIO, not DMA) to/from the TPM device, we observed that the Slave Select pin can be pulled Low during data transfer and set to High when data transfer is completed, and therefore we believe the SS pin is not hindering the data transfer, and afterwards, when we proceed to monitor the SPI clock pin, we observed that there is no clock signal comes out from the pin at all, as a result, we suspect that the failure to write to a TPM register is due to no SPI clock signal to the TPM device during data transfer.&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;When investigating why there is no SPI clock signal generated for the TPM device, we noticed that the clock enable function tpm_tis_clkrun_enable()in the TPM TIS driver (kernel version 4.14.78) supports only LPC bus on Intel platform but not the ECSPI bus on NXP IMX8M platform. It looks like the current TPM TIS driver is missing the implementation to support the enable/disable of clock signals from ECSPI bus to the TPM device during data transfer. Below is the code of function tpm_tis_clkrun_enable(),&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;static void tpm_tis_clkrun_enable(struct tpm_chip *chip, bool value)&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;{&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; struct tpm_tis_data *data = dev_get_drvdata(&amp;amp;chip-&amp;gt;dev);&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; u32 clkrun_val;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; if (!IS_ENABLED(CONFIG_X86) || !is_bsw() ||&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; !data-&amp;gt;ilb_base_addr)&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; return;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; if (value) {&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; data-&amp;gt;clkrun_enabled++;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; if (data-&amp;gt;clkrun_enabled &amp;gt; 1)&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; return;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; clkrun_val = ioread32(data-&amp;gt;ilb_base_addr + LPC_CNTRL_OFFSET);&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Disable LPC CLKRUN# */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; clkrun_val &amp;amp;= ~LPC_CLKRUN_EN;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; iowrite32(clkrun_val, data-&amp;gt;ilb_base_addr + LPC_CNTRL_OFFSET);&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; * Write any random value on port 0x80 which is on LPC, to make&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; * sure LPC clock is running before sending any TPM command.&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; outb(0xCC, 0x80);&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;} else {&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; data-&amp;gt;clkrun_enabled--;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; if (data-&amp;gt;clkrun_enabled)&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; return;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; clkrun_val = ioread32(data-&amp;gt;ilb_base_addr + LPC_CNTRL_OFFSET);&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Enable LPC CLKRUN# */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;clkrun_val |= LPC_CLKRUN_EN;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; iowrite32(clkrun_val, data-&amp;gt;ilb_base_addr + LPC_CNTRL_OFFSET);&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; * Write any random value on port 0x80 which is on LPC, to make&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; * sure LPC clock is running before sending any TPM command.&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; */&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; outb(0xCC, 0x80);&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; }&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;}&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;The schematic of IMX8M ECSPI2 pin interface:&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/81410i2AE029633F7E1555/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;The schematic of TPM device interface to the IMX8M ECSPI2:&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/81411i2925F43624197AAD/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;The ECSPI2 configurations in the device tree file is as shown below:&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;pinctrl_ecspi2: ecspi2grp {&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; fsl,pins = &amp;lt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x19&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x19&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x19&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x19&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x17059&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;};&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;pinctrl_ecspi2_cs: ecspi2cs {&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; fsl,pins = &amp;lt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;//&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x82&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x19&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;};&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;amp;ecspi2 {&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; #address-cells = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; #size-cells = &amp;lt;0&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; fsl,spi-num-chipselects = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; cs-gpios = &amp;lt;&amp;amp;gpio5 13 GPIO_ACTIVE_LOW&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;//&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; cs-gpios = &amp;lt;0&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; pinctrl-names = "default";&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; pinctrl-0 = &amp;lt;&amp;amp;pinctrl_ecspi2 &amp;amp;pinctrl_ecspi2_cs&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; dmas = &amp;lt;&amp;amp;sdma1 3 7 0&amp;gt;, &amp;lt;&amp;amp;sdma1 4 7 0&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; dma-names = "rx", "tx";&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; status = "okay";&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; tpm0: slb9670@0 {&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; compatible = "infineon,slb9670";&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; reg = &amp;lt;0&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; resets = &amp;lt;&amp;amp;tpm_reset&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; spi-max-frequency = &amp;lt;38000000&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; interrupt-parent = &amp;lt;&amp;amp;gpio3&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; interrupts = &amp;lt;3 IRQ_TYPE_LEVEL_LOW&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; status = "okay";&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; };&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;};&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;&lt;SPAN style="font-size: 9.0pt;"&gt;Really appreciate if someone can help point out what could have done wrong or can provide any solution or patch to this problem.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 17 May 2019 03:54:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Initialization-of-iMX8M-ECSPI2-TPM-2-0-device-Infineon-SLB9670/m-p/897616#M135541</guid>
      <dc:creator>yuklin_soo</dc:creator>
      <dc:date>2019-05-17T03:54:25Z</dc:date>
    </item>
    <item>
      <title>Re: Initialization of iMX8M ECSPI2 TPM 2.0 device Infineon SLB9670 failed when running TPM self test</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Initialization-of-iMX8M-ECSPI2-TPM-2-0-device-Infineon-SLB9670/m-p/897617#M135542</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I want to take back my previous claim that there are no signals come out from the SCLK pin, after adjusting my oscilloscope bandwidth to full, I am now able to see the SPI clock signals sent to the TPM device.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Another thing I noticed is that, when data is transferred between the SPI master and the TPM slave device during the TPM driver initialization:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;SPI MOSI - is set to HIGH and data bits sent through this line are superimposed on the 3.3V signal&lt;/P&gt;&lt;P&gt;SPI MISO - is set to LOW and data bits sent through this line properly&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;When initialization process completed and the SPI interface is idle,&lt;/P&gt;&lt;P&gt;SPI MOSI - is idle HIGH&lt;/P&gt;&lt;P&gt;SPI MISO - is idle LOW&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The current issue is that the TPM driver is able to read from a TPM register (through MISO) and Not able to write to a TPM register (though MOSI). Therefore, it seems the problem is on the MOSI line, is it because the data is sent through a MOSI line which is always at logic level HIGH, and that is causing the TPM device to ignore the data sent?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 May 2019 09:29:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Initialization-of-iMX8M-ECSPI2-TPM-2-0-device-Infineon-SLB9670/m-p/897617#M135542</guid>
      <dc:creator>yuklin_soo</dc:creator>
      <dc:date>2019-05-21T09:29:43Z</dc:date>
    </item>
    <item>
      <title>Re: Initialization of iMX8M ECSPI2 TPM 2.0 device Infineon SLB9670 failed when running TPM self test</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Initialization-of-iMX8M-ECSPI2-TPM-2-0-device-Infineon-SLB9670/m-p/897618#M135543</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Alex&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;first one can try with ecspi2 example without sdma :&lt;/P&gt;&lt;P&gt;linux-imx6/arch/arm64/boot/dts/freescale/imx8mq-nitrogen8m.dts&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://github.com/boundarydevices/linux-imx6/blob/boundary-imx_4.14.x_2.0.0_ga/arch/arm64/boot/dts/freescale/imx8mq-nitrogen8m.dts" title="https://github.com/boundarydevices/linux-imx6/blob/boundary-imx_4.14.x_2.0.0_ga/arch/arm64/boot/dts/freescale/imx8mq-nitrogen8m.dts"&gt;linux-imx6/imx8mq-nitrogen8m.dts at boundary-imx_4.14.x_2.0.0_ga · boundarydevices/linux-imx6 · GitHub&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regarding sdma, one can recheck sdma ecspi2 channel numbers in&amp;nbsp;Table 7-3. SDMA1 event mapping&lt;/P&gt;&lt;P&gt;i.MX8MDQ Reference Manual. Use sdma linux dts documentation&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://github.com/boundarydevices/linux-imx6/blob/boundary-imx_4.14.x_2.0.0_ga/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt" title="https://github.com/boundarydevices/linux-imx6/blob/boundary-imx_4.14.x_2.0.0_ga/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt"&gt;linux-imx6/fsl-imx-sdma.txt at boundary-imx_4.14.x_2.0.0_ga · boundarydevices/linux-imx6 · GitHub&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;and sai1 sdma example (channel number can be found in Table 7-4. SDMA2 event mapping)&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://github.com/boundarydevices/linux-imx6/blob/boundary-imx_4.14.x_2.0.0_ga/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts" title="https://github.com/boundarydevices/linux-imx6/blob/boundary-imx_4.14.x_2.0.0_ga/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts"&gt;linux-imx6/fsl-imx8mq-evk.dts at boundary-imx_4.14.x_2.0.0_ga · boundarydevices/linux-imx6 · GitHub&lt;/A&gt;&amp;nbsp;&lt;BR /&gt;&lt;A href="https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf" target="test_blank"&gt;https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 24 May 2019 10:14:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Initialization-of-iMX8M-ECSPI2-TPM-2-0-device-Infineon-SLB9670/m-p/897618#M135543</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2019-05-24T10:14:04Z</dc:date>
    </item>
    <item>
      <title>Re: Initialization of iMX8M ECSPI2 TPM 2.0 device Infineon SLB9670 failed when running TPM self test</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Initialization-of-iMX8M-ECSPI2-TPM-2-0-device-Infineon-SLB9670/m-p/897619#M135544</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for the reply.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The ECSPI2 data transfer is using the interrupt-driven method (without SDMA).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I commented out the below two lines (dmas):&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;&amp;amp;ecspi2 {&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; #address-cells = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; #size-cells = &amp;lt;0&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; fsl,spi-num-chipselects = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; cs-gpios = &amp;lt;&amp;amp;gpio5 13 GPIO_ACTIVE_LOW&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;//&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; cs-gpios = &amp;lt;0&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; pinctrl-names = "default";&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; pinctrl-0 = &amp;lt;&amp;amp;pinctrl_ecspi2 &amp;amp;pinctrl_ecspi2_cs&amp;gt;;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;//&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;dmas = &amp;lt;&amp;amp;sdma1 3 7 0&amp;gt;, &amp;lt;&amp;amp;sdma1 4 7 0&amp;gt;;&amp;nbsp; &amp;nbsp;&amp;lt; == commented out&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;//&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;dma-names = "rx", "tx";&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;lt; == commented out&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; status = "okay";&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;and now I am able to see the tpm0 device&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;# ls -l /dev/tpm*&lt;BR /&gt;crw------- 1 root root 10, 224 May 24 11:56 /dev/tpm0&lt;BR /&gt;crw------- 1 root root 252, 65536 May 24 11:56 /dev/tpmrm0&lt;BR /&gt;# cat /proc/interrupts | grep tpm&lt;BR /&gt;137: 0 0 0 0 gpio-mxc 3 Level tpm0&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;#&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;These two lines were previously added to suppress the error message:&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;[&amp;nbsp; &amp;nbsp;12.728854] spi_imx 30830000.ecspi: dma setup error -19, use pio&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px; margin: 0px 0px 0.0001pt;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit; font-size: 9pt;"&gt;Besides that, I went through the MCIMX51RM document, and found the DATA CTL field in CONFIGREG, updated the SPI driver to make sure that the ECSPI2 (SPI 1 channel) is activated and set the inactive state of the MOSI line to stay&amp;nbsp;Low.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 24 May 2019 12:21:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Initialization-of-iMX8M-ECSPI2-TPM-2-0-device-Infineon-SLB9670/m-p/897619#M135544</guid>
      <dc:creator>yuklin_soo</dc:creator>
      <dc:date>2019-05-24T12:21:46Z</dc:date>
    </item>
    <item>
      <title>Re: Initialization of iMX8M ECSPI2 TPM 2.0 device Infineon SLB9670 failed when running TPM self test</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Initialization-of-iMX8M-ECSPI2-TPM-2-0-device-Infineon-SLB9670/m-p/1185157#M165104</link>
      <description>&lt;P&gt;HI，&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;I　got a question about the ECSPI2 clock. I'm aslo using ECSPI2, and found that no clock output.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;How do you fix the no clock problem ? just set the &lt;SPAN&gt;oscilloscope ?&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 18 Nov 2020 10:35:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Initialization-of-iMX8M-ECSPI2-TPM-2-0-device-Infineon-SLB9670/m-p/1185157#M165104</guid>
      <dc:creator>jiangyaqiang</dc:creator>
      <dc:date>2020-11-18T10:35:32Z</dc:date>
    </item>
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